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| ? 2008-2014 microchip technology inc. ds70000318g-page 1 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 operating conditions 3.0v to 3.6v, -40oc to +150oc, dc to 20 mips 3.0v to 3.6v, -40oc to +125oc, dc to 40 mips 3.0v to 3.6v, -40oc to +85oc, dc to 50 mips core: 16-bit dspic33f cpu code-efficient (c and assembly) architecture two 40-bit wide accumulators single-cycle (mac/mpy) with dual data fetch single-cycle mixed-sign mul plus hardware divide 32-bit multiply support clock management 2.0% internal oscillator programmable plls and oscillator clock sources fail-safe clock monitor (fscm) independent watchdog timer (wdt) fast wake-up and start-up power management low-power management modes (sleep, idle, doze) integrated power-on reset and brown-out reset high-speed pwm up to four pwm pairs with independent timing dead time for rising and falling edges 1.04 ns pwm resolution pwm support for: - dc/dc, ac/dc, inverters, pfc and lighting programmable fault inputs flexible trigger configurations for adc conversions advanced analog features adc module: - 10-bit resolution with up to 2 successive approximation register (sar) converters (4 msps) and up to six sample-and-hold (s&h) circuits - up to 12 input channels grouped into six conversion pairs, plus two voltage reference monitoring inputs - dedicated result buffer for each analog channel flexible and independent adc trigger sources advanced analog features (continued) up to four high-speed comparators with direct connection to the pwm module: - programmable references with 1024 voltage points timers/output compare/input capture three general purpose timers: - three 16-bit and one 32-bit timer/counter two output compare (oc) modules two input capture (ic) modules peripheral pin select (pps) to allow function remap communication interfaces uart module (12.5 mbps): - with support for lin/j2602 protocols and irda ? 4-wire spi module i 2 c? module (up to 1 mbaud) with smbus support pps to allow function remap input/output sink/source 18 ma on 8 pins, 10 ma on 10 pins and 6 ma on 17 pins 5v tolerant pins selectable open-drain and pull-ups external interrupts on up to 30 i/o pins qualification and class b support aec-q100 revg (grade 1, -40oc to +125oc) aec-q100 revg (grade 0, -40oc to +150oc) class b safety library, iec 60730, vde certified 6x6x0.5 mm uqfn package designed and optimized to ease ipc9592a 2nd level temperature cycle qualification debugger development support in-circuit and in-application programming two breakpoints ieee 1149.2-compatible (jtag) boundary scan trace and run-time watch 16-bit digital signal controllers (up to 16-kbyte flash and up to 2-kbyte sram) with high-speed pwm, adc and comparators downloaded from: http:///
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 2 ? 2008-2014 microchip technology inc. dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 product families the device names, pin counts, memory sizes and peripheral availability of each device are listed below. the following pages show their pinout diagrams. table 1: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 controller families device pins program flash memory (kbytes) ram (bytes) remappable peripherals dac output i 2 c? adc i/o pins packages remappable pins 16-bit timer input capture output compare uart spi pwm ( 2 ) analog comparator external interrupts ( 3 ) sars sample-and-hold (s&h) circuit analog-to-digital inputs dspic33fj06gs101 18 6 256 8 2 0 1 1 1 2x2 ( 1 ) 0 3 0 1 1 3 6 13 soic dspic33fj06gs102 28 6 256 16 2 0 1 1 1 2x2 0 3 0 1 1 3 6 21 spdip, soic, qfn-s dspic33fj06gs202 28 6 1k 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 spdip, soic, qfn-s dspic33fj16gs402 28 16 2k 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 spdip, soic, qfn-s dspic33fj16gs404 44 16 2k 30 3 2 2 1 1 3x2 0 3 0 1 1 4 8 35 qfn, tqfp, vtla dspic33fj16gs502 28 16 2k 16 3 2 2 1 1 4x2 ( 1 ) 431126821spdip , soic, qfn-s, uqfn dspic33fj16gs504 44 16 2k 30 3 2 2 1 1 4x2 ( 1 ) 4 3 1 1 2 6 12 35 qfn, tqfp, vtla note 1: the pwm4h:pwm4l pins are remappable. 2: the pwm fault pins and pwm synchronization pins are remappable. 3: only two out of three interrupts are remappable. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 3 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pin diagrams 18-pin soic 28-pin soic, spdip dspic33fj06gs101 mclr an0/ra0 an1/ra1 v dd v ss an2/ra2 tdo/rp5 (1) /cn5/rb5 tms/pgec2/rp4 (1) /cn4/rb4 tck/pged2/int0/rp3 (1) /cn3/rb3 v cap osc2/clko/an7/rp2 (1) /cn2/rb2 osc1/clki/an6/rp1 (1) /cn1/rb1 v ss pgec1/sda1/rp7 (1) /cn7/rb7 pged1/tdi/scl1/rp6 (1) /cn6/rb6 an3/rp0 (1) /cn0/rb0 12 3 4 5 6 7 8 9 1817 16 15 14 13 12 11 10 pwm1l/ra3 pwm1h/ra4 mclr pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 rp12 (1) /cn12/rb12 rp11 (1) /cn11/rb11 v ss v dd an0/ra0 an1/ra1 av dd av ss an2/ra2 pged3/rp8 (1) /cn8/rb8 pgec3/rp15 (1) /cn15/rb15 tms/pgec2/rp4 (1) /cn4/rb4 tck/pged2/int0/rp3 (1) /cn3/rb3 v cap osc2/clko/rp2 (1) /cn2/rb2 osc1/clkin/rp1 (1) /cn1/rb1 v ss tdo/rp5 (1) /cn5/rb5 pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 an5/rp10 (1) /cn10/rb10 an4/rp9 (1) /cn9/rb9 an3/rp0 (1) /cn0/rb0 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 28-pin spdip, soic mclr pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/rp12 (1) /cn12/rb12 tms/rp11 (1) /cn11/rb11 v ss v dd an0/cmp1a/ra0 an1/cmp1b/ra1 av dd av ss an2/cmp1c/cmp2a/ra2 pged3/rp8 (1) /cn8/rb8 pgec3/rp15 (1) /cn15/rb15 pgec2/extref/rp4 (1) /cn4/rb4 pged2/dacout/int0/rp3 (1) /cn3/rb3 v cap osc2/clko/rp2 (1) /cn2/rb2 osc1/clkin/rp1 (1) /cn1/rb1 v ss tdo/rp5 (1) /cn5/rb5 pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 an5/cmp2d/rp10 (1) /cn10/rb10 an4/cmp2c/rp9 (1) /cn9/rb9 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 = pins are up to 5v tolerant = pins are up to 5v tolerant = pins are up to 5v tolerant dspic33fj06gs102 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 dspic33fj06gs202 12 3 4 5 6 7 8 9 10 11 12 2827 26 25 24 23 22 21 20 19 18 17 1314 1615 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 4 ? 2008-2014 microchip technology inc. pin diagrams (continued) 28-pin spdip, soic 28-pin spdip, soic mclr pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v ss v dd an0/ra0 an1/ra1 av dd av ss an2/ra2 pged3/rp8 (1) /cn8/rb8 pgec3/rp15/cn15/rb15 pgec2/rp4 (1) /cn4/rb4 pged2/int0/rp3 (1) /cn3/rb3 v cap osc2/clko/an7/rp2 (1) /cn2/rb2 osc1/clkin/an6/rp1 (1) /cn1/rb1 v ss tdo/rp5 (1) /cn5/rb5 pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 an5/rp10 (1) /cn10/rb10 an4/rp9 (1) /cn9/rb9 an3/rp0 (1) /cn0/rb0 mclr pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v ss v dd an0/cmp1a/ra0 an1/cmp1b/ra1 av dd av ss an2/cmp1c/cmp2a/ra2 cn8/rb8/pged3/rp8 (1) /cn8/rb8 pgec3/rp15 (1) /cn15/rb15 pgec2/extref/rp4 (1) /cn4/rb4 pged2/dacout/int0/rp3 (1) /cn3/rb3 v cap osc2/clko/an7/cmp3d/cmp4b/rp2 (1) /cn2/rb2 osc1/clkin/an6/cmp3c/cmp4a/rp1 (1) /cn1/rb1 v ss tdo/rp5 (1) /cn5/rb5 pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 an5/cmp2d/cmp3b/rp10 (1) /cn10/rb10 an4/cmp2c/cmp3a/rp9 (1) /cn9/rb9 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 = pins are up to 5v tolerant = pins are up to 5v tolerant dspic33fj16gs402 2827 26 25 24 23 22 21 20 19 18 17 16 15 12 3 4 5 6 7 8 9 10 11 12 13 14 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. dspic33fj16gs502 12 3 4 5 6 7 8 9 10 11 12 13 2827 26 25 24 23 22 21 20 19 18 17 16 14 15 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 5 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pin diagrams (continued) 28-pin qfn-s (2) 10 11 23 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj06gs102 pged2/int0/rp3 (1) /cn3/rb3 5 4 av dd av ss pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/rp12 (1) /cn12/rb12 tms/rp11 (1) /cn11/rb11 v ss v cap pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 tdo/rp5 (1) /cn5/rb5 pgec3/rp15 (1) /cn15/rb15 mclr an0/ra0 an1/ra1 an2/ra2 an3/rp0 (1) /cn0/rb0 an4/rp9 (1) /cn9/rb9 an5/rp10 (1) /cn10/rb10 v ss osc1/clkin/rp1 (1) /cn1/rb1 osc2/clko/rp2 (1) /cn2/rb2 pgec2/rp4 (1) /cn4/rb4 v dd pged3/rp8 (1) /cn8/rb8 10 11 23 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj06gs202 pged2/dacout/int0/rp3 (1) /cn3/rb3 5 4 av dd av ss pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/rp12 (1) /cn12/rb12 tms/rp11 (1) /cn11/rb11 v ss v cap pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 tdo/rp5 (1) /cn5/rb5 pgec3/rp15 (1) /cn15/rb15 mclr an0/cmp1a/ra0 an1/cmp1b/ra1 an2/cmp1c/cmp2a/ra2 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 an4/cmp2c/rp9 (1) /cn9/rb9 an5/cmp2d/rp10 (1) /cn10/rb10 v ss osc1/clkin/rp1 (1) /cn1/rb1 osc2/clko/rp2 (1) /cn2/rb2 pgec2/extref/rp4 (1) /cn4/rb4 v dd pged3/rp8 (1) /cn8/rb8 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant = pins are up to 5v tolerant 28-pin qfn-s downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 6 ? 2008-2014 microchip technology inc. pin diagrams (continued) 28-pin qfn-s (2) 10 11 23 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj16gs402 pged2/int0/rp3 (1) /cn3/rb3 5 4 av dd av ss pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v ss v cap pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 tdo/rp5 (1) /cn5/rb5 pgec3/rp15 (1) /cn15/rb15 mclr an0/ra0 an1/ra1 an2/ra2 an3/rp0 (1) /cn0/rb0 an4/rp9 (1) /cn9/rb9 an5/rp10 (1) /cn10/rb10 v ss osc1/clkin/an6/rp1 (1) /cn1/rb1 osc2/clko/an7/rp2 (1) /cn2/rb2 pgec2/rp4 (1) /cn4/rb4 v dd pged3/rp8 (1) /cn8/rb8 10 11 23 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj16gs502 pged2/dacout/int0/rp3 (1) /cn3/rb3 5 4 av dd av ss pwm1l/ra3 pwm1h/ra4 pwm2l/rp14 (1) /cn14/rb14 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v ss v cap pgec1/sda/rp7 (1) /cn7/rb7 pged1/tdi/scl/rp6 (1) /cn6/rb6 tdo/rp5 (1) /cn5/rb5 pgec3/rp15 (1) /cn15/rb15 mclr an0/cmp1a/ra0 an1/cmp1b/ra1 an2/cmp1c/cmp2a/ra2 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 an4/cmp2c/cmp3a/rp9 (1) /cn9/rb9 an5/cmp2d/cmp3b/rp10 (1) /cn10/rb10 v ss osc1/clkin/an6/cmp3c/cmp4a/rp1 (1) /cn1/rb1 osc2/clko/an7/cmp3d/cmp4b/rp2 (1) /cn2/rb2 pgec2/extref/rp4 (1) /cn4/rb4 v dd pged3/rp8 (1) /cn8/rb8 28-pin qfn-s, uqfn (2,3) = pins are up to 5v tolerant = pins are up to 5v tolerant note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 3: this package is available only in extended temper ature and not industrial temperature (applies to dspic33fj16gs502 uqfn package only). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 7 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pin diagrams (continued) 44-pin vtla (2) an4/rp9 (1) /cn9/rb9 an5/rp10 (1) /cn10/rb10 osc1/clki/an6/rp1 (1) /cn1/rb1 osc2/clko/an7/rp2 (1) /cn2/rb2 rp17 (1) /cn17/rc1 rp26 (1) /cn26/rc10 v dd rp25 (1) /cn25/rc9 v ss pged1/tdi/scl/rp6 (1) /cn6/rb6 rp18 (1) /cn18/rc2 pgec3/rp15 (1) /cn15/rb15 v dd pgec2/rp4 (1) /cn4/rb4 rp24 (1) /cn24/rc8 v ss tdo/rp5 (1) /cn5/rb5 pged3/rp8 (1) /cn8/rb8 rp23 (1) /cn23/rc7 pged2/int0/rp3 (1) /cn3/rb3 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v cap v ss rp20 (1) /cn20/rc4 rp19 (1) /cn19/rc3 rp22 (1) /cn22/rc6 rp21 (1) /cn21/rc5 pgec1/sda/rp7 (1) /cn7/rb7 pwm2l/rp14 (1) /cn14/rb14 an3/rp0 (1) /cn0/rb0 an2/ra2 an1/ra1 an0/ra0 mclr rp29 (1) /cn29/rc13 av dd av ss pwm1l/ra3 pwm1h/ra4 rp16 (1) /cn16/rc0 rp28 (1) /cn28/rc12 rp27 (1) /cn27/rc11 = pins are up to 5v tolerant 1 12 41 40 39 38 37 36 35 34 2 3 4 5 6 7 8 30 29 28 27 26 25 24 23 13 14 15 16 17 18 19 9 10 11 22 20 21 3332 31 42 43 44 dspic33fj16gs404 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 8 ? 2008-2014 microchip technology inc. pin diagrams (continued) 44-pin vtla (2) an4/cmp2c/cmp3a/rp9 (1) /cn9/rb9 an5/cmp2d/cmp3b/rp10 (1) /cn10/rb10 osc1/clki/an6/cmp3c/cmp4a/rp1 (1) /cn1/rb1 osc2/clko/an7/cmp3d/cmp4b/rp2 (1) /cn2/rb2 an8/cmp4c/rp17 (1) /cn17/rc1 an10/rp26 (1) /cn26/rc10 v dd an11/rp25 (1) /cn25/rc9 v ss pged1/tdi/scl/rp6 (1) /cn6/rb6 an9/extref/cmp4d/rp18 (1) /cn18/rc2 pgec3/rp15 (1) /cn15/rb15 v dd pgec2/rp4 (1) /cn4/rb4 rp24 (1) /cn24/rc8 v ss tdo/rp5 (1) /cn5/rb5 pged3/rp8 (1) /cn8/rb8 rp23 (1) /cn23/rc7 pged2/dacout/int0/rp3 (1) /cn3/rb3 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v cap v ss rp20 (1) /cn20/rc4 rp19 (1) /cn19/rc3 rp22 (1) /rn22/rc6 rp21 (1) /cn21/rc5 pgec1/sda/rp7 (1) /cn7/rb7 pwm2l/rp14 (1) /cn14/rb14 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 an2/cmp1c/cmp2a/ra2 an1/cmp1b/ra1 an0/cmp1a/ra0 mclr rp29 (1) /cn29/rc13 av dd av ss pwm1l/ra3 pwm1h/ra4 rp16 (1) /cn16/rc0 rp28 (1) /cn28/rc12 rp27 (1) /cn27/rc11 = pins are up to 5v tolerant 1 12 41 40 39 38 37 36 35 34 2 3 4 5 6 7 8 30 29 28 27 26 25 24 23 13 14 15 16 17 18 19 9 10 11 22 20 21 3332 31 42 43 44 dspic33fj16gs504 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 9 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pin diagrams (continued) 44-pin qfn (2) 44 dspic33fj16gs404 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 6 22 33 34 an4/rp9 (1) /cn9/rb9 an5/rp10 (1) /cn10/rb10 osc1/clki/an6/rp1 (1) /cn1/rb1 osc2/clko/an7/rp2 (1) /cn2/rb2 rp17 (1) /cn17/rc1 rp26 (1) /cn26/rc10 v dd rp25 (1) /cn25/rc9 v ss pged1/tdi/scl/rp6 (1) /cn6/rb6 rp18 (1) /cn18/rc2 pgec3/rp15 (1) /cn15/rb15 v dd pgec2/rp4 (1) /cn4/rb4 rp24 (1) /cn24/rc8 v ss tdo/rp5 (1) /cn5/rb5 pged3/rp8 (1) /cn8/rb8 rp23 (1) /cn23/rc7 pged2/int0/rp3 (1) /cn3/rb3 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v cap v ss rp20 (1) /cn20/rc4 rp19 (1) /cn19/rc3 rp22 (1) /cn22/rc6 rp21 (1) /cn21/rc5 pgec1/sda/rp7 (1) /cn7/rb7 pwm2l/rp14 (1) /cn14/rb14 an3/rp0 (1) /cn0/rb0 an2/ra2 an1/ra1 an0/ra0 mclr rp29 (1) /cn29/rc13 av dd av ss pwm1l/ra3 pwm1h/ra4 rp16 (1) /cn16/rc0 rp28 (1) /cn28/rc12 rp27 (1) /cn27/rc11 = pins are up to 5v tolerant note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 10 ? 2008-2014 microchip technology inc. pin diagrams (continued) 44-pin qfn (2) 44 dspic33fj16gs504 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 45 7 8 9 10 11 12 32 31 6 22 33 34 an4/cmp2c/cmp3a/rp9 (1) /cn9/rb9 an5/cmp2d/cmp3b/rp10 (1) /cn10/rb10 osc1/clki/an6/cmp3c/cmp4a/rp1 (1) /cn1/rb1 osc2/clko/an7/cmp3d/cmp4b/rp2 (1) /cn2/rb2 an8/cmp4c/rp17 (1) /cn17/rc1 an10/rp26 (1) /cn26/rc10 v dd an11/rp25 (1) /cn25/rc9 v ss pged1/tdi/scl/rp6 (1) /cn6/rb6 an9/extref/cmp4d/rp18 (1) /cn18/rc2 pgec3/rp15 (1) /cn15/rb15 v dd pgec2/rp4 (1) /cn4/rb4 rp24 (1) /cn24/rc8 v ss tdo/rp5 (1) /cn5/rb5 pged3/rp8 (1) /cn8/rb8 rp23 (1) /cn23/rc7 pged2/dacout/int0/rp3 (1) /cn3/rb3 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v cap v ss rp20 (1) /cn20/rc4 rp19 (1) /cn19/rc3 rp22 (1) /rn22/rc6 rp21 (1) /cn21/rc5 pgec1/sda/rp7 (1) /cn7/rb7 pwm2l/rp14 (1) /cn14/rb14 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 an2/cmp1c/cmp2a/ra2 an1/cmp1b/ra1 an0/cmp1a/ra0 mclr rp29 (1) /cn29/rc13 av dd av ss pwm1l/ra3 pwm1h/ra4 rp16 (1) /cn16/rc0 rp28 (1) /cn28/rc12 rp27 (1) /cn27/rc11 = pins are up to 5v tolerant note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 11 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pin diagrams (continued) 44-pin tqfp 1011 23 4 5 6 1 18 19 20 21 2212 13 14 15 38 8 7 4443 42 41 40 39 16 17 29 30 31 32 3323 24 25 26 27 28 3634 35 9 37 pged1/tdi/scl/rp6 (1) /cn6/rb6 rp18 (1) /cn18/rc2 pgec3/rp15 (1) /cn15/rb15 v dd pgec2/rp4 (1) /cn4/rb4 rp16 (1) /cn16/rc0 v ss tdo/rp5 (1) /cn5/rb5 pged3/rp8 (1) /cn8/rb8 rp23 (1) /cn23/rc7 an3/rp0 (1) /cn0/rb0 an2/ra2 an1/ra1 an0/ra0 mclr rp29 (1) /cn29/rc13 av dd av ss pwm1l/ra3 pwm1h/ra4 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v ss v cap rp19 (1) /cn19/rc3 rp22 (1) /cn22/rc6 rp21 (1) /cn21/rc5 pgec1/sda/rp7 (1) /cn7/rb7 an4/rp9 (1) /cn9/rb9 an5/rp10 (1) /cn10/rb10 osc1/clki/an6/rp1 (1) /cn1/rb1 osc2/clko/an7/rp2 (1) /cn2/rb2 rp17 (1) /cn17/rc1 rp20 (1) /cn20/rc4 v dd v ss rp27 (1) /cn27/rc11 rp28 (1) /cn28/rc12 pged2/int0/rp3 (1) /cn3/rb3 dspic33fj16gs404 pwm2l/rp14 (1) /cn14/rb14 rp24 (1) /cn24/rc8 rp25 (1) /cn25/rc9 rp26 (1) /cn26/rc10 = pins are up to 5v tolerant note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 12 ? 2008-2014 microchip technology inc. pin diagrams (continued) 44-pin tqfp 1011 23 4 5 6 1 18 19 20 21 2212 13 14 15 38 8 7 4443 42 41 40 39 16 17 29 30 31 32 3323 24 25 26 27 28 3634 35 9 37 pged1/tdi/scl/rp6 (1) /cn6/rb6 an9/extref/cmp4d/rp18 (1) /cn18/rc2 pgec3/rp15 (1) /cn15/rb15 v dd pgec2/rp4 (1) /cn4/rb4 rp16 (1) /cn16/rc0 v ss tdo/rp5 (1) /cn5/rb5 pged3/rp8 (1) /cn8/rb8 rp23 (1) /cn23/rc7 an3/cmp1d/cmp2b/rp0 (1) /cn0/rb0 an2/cmp1c/cmp2a/ra2 an1/cmp1b/ra1 an0/cmp1a/ra0 mclr rp29 (1) /cn29/rc13 av dd av ss pwm1l/ra3 pwm1h/ra4 pwm2h/rp13 (1) /cn13/rb13 tck/pwm3l/rp12 (1) /cn12/rb12 tms/pwm3h/rp11 (1) /cn11/rb11 v ss v cap rp19 (1) /cn19/rc3 rp22 (1) /cn22/rc6 rp21 (1) /cn21/rc5 pgec1/sda/rp7 (1) /cn7/rb7 an4/cmp2c/cmp3a/rp9 (1) /cn9/rb9 an5/cmp2d/cmp3b/rp10 (1) /cn10/rb10 osc1/clki/an6/cmp3c/cmp4a/rp1 (1) /cn1/rb1 osc2/clko/an7/c mp3d/cmp4b/rp2 (1) /cn2/rb2 an8/cmp4c/rp17 (1) /cn17/rc1 rp20 (1) /cn20/rc4 v dd v ss rp27 (1) /cn27/rc11 rp28 (1) /cn28/rc12 pged2/dacout/int0/rp3 (1) /cn3/rb3 dspic33fj16gs504 pwm2l/rp14 (1) /cn14/rb14 rp24 (1) /cn24/rc8 an11/rp25 (1) /cn25/rc9 an10/rp26 (1) /cn26/rc10 = pins are up to 5v tolerant note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 13 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table of contents dspic33fj06gs101/x02 and dspic33fj16gsx02/x 04 product families............................................ ..................... ........................ 2 1.0 device overview ....................................................... ...................................................... ........................................................... 17 2.0 guidelines for getting started with 16-bit digital signal controllers .................. ..................................... ................................... 21 3.0 cpu.............................................................................................. .............................................................................................. 31 4.0 memory organization .......................................... ................................................... ............ ........................................................ 43 5.0 flash program memory.................................................................. ...................................... ...................................................... 83 6.0 resets ......................................................................................... ............................ .................................................................. 89 7.0 interrupt controller ................................................ ........................................................ ............................................................. 97 8.0 oscillator configuration .................................. ........................................................................................................... ............ 135 9.0 power-saving features............................................................ ........................................... ..................................................... 147 10.0 i/o ports ....................................................................................... ........................... ................................................................. 155 11.0 timer1 ......................................................................... ........................................................................................................... .. 183 12.0 timer2/3 features ................................................................... ...................................... .......................................................... 185 13.0 input capture............................................ ................................................... ............... .............................................................. 191 14.0 output compare.................................................... ......................................................... .......................................................... 193 15.0 high-speed pwm............................................................................. ................................ ........................................................ 197 16.0 serial peripheral interface (spi)........................................ .................................................. ..................................................... 219 17.0 inter-integrated circuit (i 2 c?) ..................................................................................................... ....................... ..................... 225 18.0 universal asynchronous receiver transmitter (uart) ............................... .......................................... .................................. 233 19.0 high-speed 10-bit analog-to-digital converter (adc) ..................... ................................................... ..................................... 239 20.0 high-speed analog comparator .................................................... ........................................... ............................................... 263 21.0 special features ................................................... ........................................................ ........................................................... 267 22.0 instruction set summary ........................................................ ............................................ ...................................................... 275 23.0 development support............................................ ................................................... ......... ....................................................... 283 24.0 electrical characteristics ........................................................ ......................................... ......................................................... 287 25.0 high-temperature electrical characteristics.......................... ...................................................... ............................................ 333 26.0 50 mips electrical characteristics ........................................... .............................................. .................................................. 341 27.0 dc and ac device characteristics graphs.................................. .................................................. .......................................... 347 28.0 packaging information................................................................ ...................................... ........................................................ 351 the microchip web site ....................................................................... .................................. ............................................................ 393 customer change notification service ....................................... ................................................... . ................................................... 393 customer support............................................... ................................................... ............. ............................................................... 393 product identification system ................................................. ........................................................................................................... 395 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 14 ? 2008-2014 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 15 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 referenced sources this device data sheet is based on the following individual chapters of the ?dspic33/pic24 family ref- erence manual? . these documents should be considered as the primary reference for the operation of a particular module or device feature. introduction (ds70197) cpu (ds70204) data memory (ds70202) program memory (ds70203) flash programming (ds70191) reset (ds70192) watchdog timer (wdt) and power-saving modes (ds70196) i/o ports (ds70193) timers (ds70205) input capture (ds70198) output compare (ds70005157) analog-to-digital converter (adc) (ds70621) uart (ds70188) serial peripheral interface (spi) (ds70206) inter-integrated circuit? (i 2 c?) (ds70000195) codeguard? security (ds70199) programming and diagnostics (ds70207) device configuration (ds70194) interrupts (part iv) (ds70300) oscillator (part iv) (ds70307) high- speed pwm module (ds70000323) high-speed 10-bit adc (ds70000321) high-speed analog comparator (ds70296) oscillator (part vi) (ds70644) note: to access the documents listed below, browse to the documentation section of the dspic33fj16gs504 product page of the microchip web site ( www.microchip.com ). in addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 16 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 17 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 1.0 device overview this document contains device-specific information for the following dspic33f digital signal controller (dsc) devices: dspic33fj06gs101 dspic33fj06gs102 dspic33fj06gs202 dspic33fj16gs402 dspic33fj16gs404 dspic33fj16gs502 dspic33fj16gs504 ds pic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices contain extensive digital signal processor (dsp) functionality with a high-performance, 16-bit microcontroller (mcu) architecture. figure 1-1 shows a general block diagram of the core and peripheral modules in the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices. ta b l e 1 - 1 lists the functions of the various pins shown in the pinout diagrams. note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to the ?dspic33f/pic24h family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest ?dspic33f/pic24h family reference manual? sections. 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 18 ? 2008-2014 microchip technology inc. figure 1-1: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 block diagram 16 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset frc/lprc oscillators regulator voltage v cap ic1 i2c1 porta instruction decode & control pch 16 program counter 23 23 24 23 pcu 16 x 16 w register array rom latch 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic address latch program memory data latch literal data 16 16 16 16 data latch address latch 16 x ram 16 y data bus x data bus dsp engine divide support 16 control signals to various blocks adc1 timers portb address generator units 1-3 cnx uart1 pwm 4 x 2 remappable pins portc spi1 oc1 oc2 analog comparators 1-4 note: not all pins or features are implemented on all device pinout c onfigurations. see pinout diagrams for the specific pins and features present on each device. pcl data latch address latch y ram ea mux instruction reg 16-bit alu ic2 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 19 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 1-1: pinout i/o descriptions pin name pin type buffer type pps capable description an0-an11 i analog no analog input channels clki clko i o st/cmos nono external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 osc2 i i/o st/cmos nono oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. cn0-cn29 i st no change notification inputs. can be software programmed for internal weak pull-ups on all inputs. ic1-ic2 i st yes capture inputs 1/2. ocfa oc1-oc2 i o st yes yes compare fault a input (for compare channels 1 and 2) compare outputs 1 through 2. int0int1 int2 ii i stst st no yes yes external interrupt 0. external interrupt 1. external interrupt 2. ra0-ra4 i/o st no porta is a bidirectional i/o port. rb0-rb15 i/o st no portb is a bidirectional i/o port. rc0-rc13 i/o st no portc is a bidirectional i/o port. rp0-rp29 i/o st no remappable i/o pins. t1ck t2ck t3ck ii i stst st yes yes yes timer1 external clock input. timer2 external clock input. timer3 external clock input. u1cts u1rts u1rx u1tx i o i o st st yes yes yes yes uart1 clear-to-send. uart1 ready-to-send. uart1 receive. uart1 transmit. sck1sdi1 sdo1 ss1 i/o i o i/o stst st yes yes yes yes synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization or frame pulse i/o. scl1sda1 i/oi/o stst nono synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. tmstck tdi tdo ii i o ttlttl ttl nono no no jtag test mode select pin. jtag test clock input pin. jtag test data input pin. jtag test data output pin. legend: cmos = cmos compatible input or output analog = analog input i = input st = schmitt trigger input with cmos levels p = power o = output ttl = transistor-transistor logic pps = peripheral pin select downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 20 ? 2008-2014 microchip technology inc. cmp1a cmp1b cmp1c cmp1d cmp2a cmp2b cmp2c cmp2d cmp3a cmp3b cmp3c cmp3d cmp4a cmp4b cmp4c cmp4d ii i i i i i i i i i i i i i i analog analog analog analog analog analog analog analog analog analog analog analog analog analog analog analog nono no no no no no no no no no no no no no no comparator 1 channel a. comparator 1 channel b. comparator 1 channel c. comparator 1 channel d. comparator 2 channel a. comparator 2 channel b. comparator 2 channel c. comparator 2 channel d. comparator 3 channel a. comparator 3 channel b. comparator 3 channel c. comparator 3 channel d. comparator 4 channel a. comparator 4 channel b. comparator 4 channel c. comparator 4 channel d. dacout o no dac output voltage. acmp1-acmp4 o yes dac trigger to pwm module. extref i analog no external voltage reference input for the reference dacs. refclko o yes refclko output signal is a postscaled derivative of the system clock. flt1-flt8 synci1-synci2 synco1 pwm1l pwm1h pwm2l pwm2h pwm3l pwm3h pwm4l pwm4h ii oo o o o o o o o stst yes yes yes nono no no no no yes yes fault inputs to pwm module. external synchronization signal to pwm master time base. pwm master time base for external device synchronization. pwm1 low output. pwm1 high output. pwm2 low output. pwm2 high output. pwm3 low output. pwm3 high output. pwm4 low output. pwm4 high output. pged1 pgec1 pged2 pgec2 pged3 pgec3 i/o i i/o i i/o i stst st st st st nono no no no no data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. mclr i/p st no master clear (reset) input. this pin is an active-low reset to the device. av dd p p no positive supply for analog modules. this pin must be connected at all times. av dd is connected to v dd . av ss p p no ground reference for analog modules. av ss is connected to v ss . v dd p no positive supply for peripheral logic and i/o pins. v cap p no cpu logic filter capacitor connection. v ss p no ground reference for logic and i/o pins. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps capable description legend: cmos = cmos compatible input or output analog = analog input i = input st = schmitt trigger input with cmos levels p = power o = output ttl = transistor-transistor logic pps = peripheral pin select downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 21 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 2.0 guidelines for getting started with 16-bit digital signal controllers 2.1 basic connection requirements getting started with the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 family of 16-bit digital signal controllers (dsc) requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names, which must always be connected: all v dd and v ss pins (see section 2.2 decoupling capacitors ) all av dd and av ss pins (regardless if adc module is not used) (see section 2.2 decoupling capacitors ) v cap (see section 2.3 capacitor on internal voltage regulator (v cap ) ) mclr pin (see section 2.4 master clear (mclr) pin ) pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 icsp? pins ) osc1 and osc2 pins when external oscillator source is used (see section 2.6 external oscillator pins ) 2.2 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss is required. consider the following criteria when using decoupling capacitors: value and type of capacitor: recommendation of 0.1 f (100 nf), 10-20v. this capacitor should be a low-esr and have resonance frequency in the range of 20 mhz and higher. it is recommended that ceramic capacitors be used. placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 22 ? 2008-2014 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including dscs to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that con- nects the power supply source to the device, and the maximum current drawn by the device in the applica- tion. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 f to 47 f. 2.3 capacitor on internal voltage regulator (v cap ) a low-esr (<5 ohms) capacitor is required on the v cap pin, which is used to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd , and must have a capacitor between 4.7 f and 10 f, 16v connected to ground. the type can be ceramic or tantalum. refer to section 24.0 electrical characteristics for additional information. the placement of this capacitor should be close to the v cap . it is recommended that the trace length not exceed one-quarter inch (6 mm). refer to section 21.2 on-chip voltage regulator for details. 2.4 master clear (mclr ) pin the mclr pin provides two specific device functions: device reset device programming and debugging. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as shown in figure 2-2 , it is recommended that the capacitor c, be isolated from the mclr pin during programming and debugging operations. place the components shown in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections dspic33f v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic v cap l1 (1) r1 10 f tantalum note 1: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 ? and the inductor capacity greater than 10 ma. where: f f cnv 2 ------------- - = f 1 2 ? lc ?? ----------------------- = l 1 2 ? fc ?? --------------------- - ?? ?? 2 = (i.e., adc conversion rate/2) note 1: r ? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r1 ? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c r1 r v dd mclr dspic33f jp downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 23 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 2.5 icsp? pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes, and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communications to the device. if such discrete components are an application requirement, they should be removed from the circuit during program- ming and debugging. alternatively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the communication channel select (i.e., pgecx/pgedx pins) programmed into the device matches the physical connections for the icsp to mplab ? icd 3 or mplab ? real ice?. for more information on icd 3 and real ice connection requirements, refer to the following documents that are available on the microchip web site. ?using mplab ? icd 3? (poster) ds51765 ?mplab ? icd 3 design advisory? ds51764 ?mplab ? real ice? in-circuit debugger user?s guide? ds51616 ?using mplab ? real ice?? (poster) ds51749 2.6 external oscillator pins many dscs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 oscillator configuration for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. a suggested layout is shown in figure 2-3 . figure 2-3: suggested placement of the oscillator circuit 2.7 oscillator value conditions on device start-up if the pll of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 mhz < f in < 8 mhz to comply with device pll start-up conditions. this means that if the external oscillator frequency is outside this range, the application must start up in the frc mode first. the default pll settings after a por with an oscillator frequency outside this range will violate the device operating speed. once the device powers up, the application firmware can initialize the pll sfrs, clkdiv, and pllfbd to a suitable value, and then perform a clock switch to the oscillator + pll clock source. note that clock switching must be enabled in the device configuration word. 13 main oscillator guard ring guard trace secondary oscillator 14 15 16 17 18 19 20 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 24 ? 2008-2014 microchip technology inc. 2.8 configuration of analog and digital pins during icsp operations if mplab icd 2, icd 3 or real ice is selected as a debugger, it automatically initializes all of the a/d input pins (anx) as digital pins, by setting all bits in the adpcfg register. the bits in the registers that correspond to the a/d pins that are initialized by mplab icd 2, icd 3, or real ice, must not be cleared by the user application firm- ware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain a/d pins as analog input pins during the debug session, the user application must clear the corresponding bits in the adpcfg register during initialization of the adc module. when mplab icd 2, icd 3, or real ice is used as a programmer, the user application firmware must correctly configure the adpcfg register. automatic initialization of these registers is only done during debugger opera- tion. failure to correctly configure the register(s) will result in all a/d pins being recognized as analog input pins, resulting in the port value being read as a logic 0 , which may affect user application functionality. 2.9 unused i/os unused i/o pins should be configured as outputs and driven to a logic-low state. alternatively, connect a 1k to 10k resistor between v ss and unused pins and drive the output to logic low. 2.10 typical application connection examples examples of typical application connections are shown in figure 2-4 through figure 2-11 . downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 25 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 2-4: digital pfc figure 2-5: boost converter implementation v ac i pfc v hv _ bus adc channel adc channel adc channel pwm output |v ac | k 1 k 2 k 3 fet dspic33fj06gs101 driver i pfc v output adc channel adc adc channel pwm k 1 k 2 k 3 fet dspic33fj06gs101 v input channel output driver downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 26 ? 2008-2014 microchip technology inc. figure 2-6: single-phase synchronous buck converter figure 2-7: multi-phase synchronous buck converter k 1 analog comp. k 2 k 7 pwm pwm adc channel adc channel 5v output i 5v 12v input dspic33fj06gs202 fet driver k 5 k 4 k 3 k 6 k 7 analog comparator analog comparator adc channel analog comparator adc channel pwm pwm pwm pwm pwm pwm 3.3v output 12v input fet driver fet driver fet driver dspic33fj06gs502 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 27 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 2-8: off-line ups adc adc adc adc adc pwm pwm pwm dspic33fj16gs504 pwm pwm pwm fet driver fet driver k 2 k 1 fet driver fet driver fet driver fet driver k 4 k 5 v bat gnd + v out + v out - full-bridge inverter push-pull converter v dc gnd fet driver adc pwm k 3 k 6 or analog comp. battery charger + downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 28 ? 2008-2014 microchip technology inc. figure 2-9: interleaved pfc v ac v out + adc channel pwm adc pwm |v ac | k 4 k 3 fet dspic33fj06gs202 driver v out - adc channel fet driver adc k 1 k 2 channel channel adc channel downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 29 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 2-10: phase-shifte d full-bridge converter v in + v in - s1 gate 4 gate 2 gate 3 gate 1 analog ground v out + v out - k 2 fet driver k 1 fet driver fet driver gate 1 gate 2 s1 gate 3 gate 4 s3 s3 gate 6 gate 5 gate 6 gate 5 dspic33fj06gs202 pwm pwm adc channel pwm adc channel downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 30 ? 2008-2014 microchip technology inc. figure 2-11: ac-to-dc power supply with pfc and three outputs (12v, 5v and 3.3v) k 4 adc channel pwm uart rx pwm pwm i zvt v hv _ bus v out isolation barrier adc channel pwmpwm pwm fet driver fet driver fet driver dspic33fj16gs504 k 6 analog comp. uart tx k 10 k 7 k 9 k 8 k 11 k 5 pwmpwm adc channel analog comparator analog comparator adc channel analog comparator adc channel pwmpwm pwm pwm pwm pwm 3.3v output 5v output i 5v 12v input fet driver fet driver fet driver fet driver i 3.3v_3 i 3.3v_2 i 3.3v_1 dspic33fj16gs504 v ac i pfc v hv _ bus |v ac | k 1 k 2 k 3 fet driver adc ch. adc ch. pwm output adc ch. pfc stage 3.3v multi-phase buck stage zvt with current doubler synchronous rectifier 5v buck stage secondary controller primary controller downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 31 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 3.0 cpu the cpu module has a 16-bit (data) modified harvard architecture with an enhanced instruction set, including significant support for dsp. the cpu has a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m x 24 bits of user program memory space. the actual amount of program memory implemented varies from device to device. a single- cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. all instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. overhead-free program loop constructs are supported using the do and repeat instructions, both of which are interruptible at any point. dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices have sixteen, 16-bit working registers in the programmers model. each of the working registers can serve as a data, address or address offset register. the sixteenth working register (w15) operates as a software stack pointer (sp) for interrupts and calls. there are two classes of instruction in the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices: mcu and dsp. these two instruction classes are seamlessly integrated into a single cpu. the instruction set includes many addressing modes and is designed for optimum c compiler efficiency. for most instructions, the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, three parameter instructions can be supported, allowing a + b = c operations to be executed in a single cycle. a block diagram of the cpu is shown in figure 3-1 , and the programmers model is shown in figure 3-2 . 3.1 data addressing overview the data space can be addressed as 32k words or 64 kbytes and is split into two blocks, referred to as x and y data memory. each memory block has its own independent address generation unit (agu). the mcu class of instructions operates solely through the x memory agu, which accesses the entire memory map as one linear data space. certain dsp instructions operate through the x and y agus to support dual operand reads, which splits the data address space into two parts. the x and y data space boundary is device-specific. overhead-free circular buffers (modulo addressing mode) are supported in both x and y address spaces. the modulo addressing removes the software boundary checking overhead for dsp algorithms. furthermore, the x agu circular addressing can be used with any of the mcu class of instructions. the x agu also supports bit-reversed addressing to greatly simplify input or output data reordering for radix-2 fft algorithms. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k program word boundary defined by the 8-bit program space visibility page (psvpag) register. the program-to-data space mapping feature allows any instruction access program space as if it were data space. 3.2 dsp engine overview the dsp engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. the barrel shifter is capable of shifting a 40-bit value up to 16 bits, right or left, in a single cycle. the dsp instructions operate seamlessly with all other instructions and have been designed for optimal real- time performance. the mac instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two w registers and accumulating and optionally saturating the result in the same cycle. this instruction functionality requires that the ram data space be split for these instructions and linear for all others. data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to cpu (ds70204) in the dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 32 ? 2008-2014 microchip technology inc. 3.3 special mcu features dspic33fj06gs101/x02 a nd dspic33fj16gsx02/x04 devices feature a 17-bit by 17-bit single-cycle multi- plier that is shared by both the mcu alu and dsp engine. the multiplier can perform signed, unsigned and mixed sign multiplication. using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (1.0). the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices support 16/16 and 32/16 divide operations, both fractional and integer. all divide instructions are iter- ative operations. they must be executed within a repeat loop, resulting in a total execution time of 19 instruction cycles. the divide operation can be interrupted during any of those 19 cycles without loss of data. a 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. the barrel shifter can be used by both mcu and dsp instructions. figure 3-1: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 cpu core block diagram instruction decode & control pch program counter 24 23 instruction reg pcu rom latch ea mux interrupt controller stack control logic loop control logic data latch address latch control signals to various blocks literal data 16 16 16 to peripheral modules data latch address latch 16 x ram y ram address generator units 16 y data bus x data bus dsp engine divide support 16 16 23 23 16 8 psv & table data access control block 16 16 16 16 program memory data latch address latch pcl 16 x 16 w register array 16-bit alu downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 33 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 3-2: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 programmers model pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators acca accb 7 0 program space visibility page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 34 ? 2008-2014 microchip technology inc. 3.4 cpu control registers register 3-1: sr: cpu status register r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r-0 r/w-0 oa ob sa ( 1 ) sb ( 1 ) oab sab ( 1 , 4 ) da dc bit 15 bit 8 r/w-0 ( 3 ) r/w-0 ( 3 ) r/w-0 ( 3 ) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 ( 2 ) ipl1 ( 2 ) ipl0 ( 2 ) ra n ov z c bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown u = unimplemented bit, read as 0 bit 15 oa: accumulator a overflow status bit 1 = accumulator a has overflowed 0 = accumulator a has not overflowed bit 14 ob: accumulator b overflow status bit 1 = accumulator b has overflowed 0 = accumulator b has not overflowed bit 13 sa: accumulator a saturation sticky status bit ( 1 ) 1 = accumulator a is saturated or has been saturated at some time 0 = accumulator a is not saturated bit 12 sb: accumulator b saturation sticky status bit ( 1 ) 1 = accumulator b is saturated or has been saturated at some time 0 = accumulator b is not saturated bit 11 oab: oa || ob combined accumulator overflow status bit 1 = accumulator a or b has overflowed 0 = neither accumulator a or b has overflowed bit 10 sab: sa || sb combined accumulator sticky status bit ( 1 , 4 ) 1 = accumulator a or b is saturated or has been saturated at some time in the past 0 = neither accumulator a or b is saturated bit 9 da: do loop active bit 1 = do loop in progress 0 = do loop not in progress bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level (ipl). the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis = 1 (intcon1<15>). 4: clearing this bit will clear sa and sb. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 35 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 7-5 ipl<2:0>: cpu interrupt priority level status bits ( 2 , 3 ) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (2s complement). it indicate s an overflow of a magnitude that causes the sign bit to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation that affects the z bit has set it at some time in the past 0 = the most recent operation that affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most significant bit (msb) of the result occurred 0 = no carry-out from the most significant bit of the result occurred register 3-1: sr: cpu status register (continued) note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level (ipl). the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis = 1 (intcon1<15>). 4: clearing this bit will clear sa and sb. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 36 ? 2008-2014 microchip technology inc. register 3-2: corcon: core control register u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 u se d t ( 1 ) dl2 dl1 dl0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 ( 2 ) psv rnd if bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown u = unimplemented bit, read as 0 bit 15-13 unimplemented: read as 0 bit 12 us: dsp multiply unsigned/signed control bit 1 = dsp engine multiplies are unsigned 0 = dsp engine multiplies are signed bit 11 edt: early do loop termination control bit ( 1 ) 1 = terminate executing do loop at end of current loop iteration 0 = no effect bit 10-8 dl<2:0>: do loop nesting level status bits 111 = 7 do loops are active 001 = 1 do loop is active 000 = 0 do loops are active bit 7 sata: acca saturation enable bit 1 = accumulator a saturation is enabled 0 = accumulator a saturation is disabled bit 6 satb: accb saturation enable bit 1 = accumulator b saturation is enabled 0 = accumulator b saturation is disabled bit 5 satdw: data space write from dsp engine saturation enable bit 1 = data space write saturation is enabled 0 = data space write saturation is disabled bit 4 accsat: accumulator saturation mode select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 ipl3: cpu interrupt priority level status bit 3 ( 2 ) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space is visible in data space 0 = program space is not visible in data space note 1: this bit will always read as 0 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 37 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 1 rnd: rounding mode select bit 1 = biased (conventional) rounding is enabled 0 = unbiased (convergent) rounding is enabled bit 0 if: integer or fractional multiplier mode select bit 1 = integer mode is enabled for dsp multiply ops 0 = fractional mode is enabled for dsp multiply ops register 3-2: corcon: core control register (continued) note 1: this bit will always read as 0 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 38 ? 2008-2014 microchip technology inc. 3.5 arithmetic logic unit (alu) the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 alu is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are 2s com- plement in nature. depending on the operation, the alu can affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. data for the alu operation can come from the w register array or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157) for information on the sr bits affected by each instruction. the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 cpu incorporates hardware support for both multipli- cation and division. this includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 3.5.1 multiplier using the high-speed, 17-bit x 17-bit multiplier of the dsp engine, the alu supports unsigned, signed or mixed sign operation in several mcu multiplication modes: 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 3.5.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. the 16-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.6 dsp engine the dsp engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 is a single-cycle instruction flow architecture; therefore, concurrent operation of the dsp engine with mcu instruction flow is not possible. however, some mcu alu and dsp engine resources can be used concurrently by the same instruction (for example, ed , edac ). the dsp engine can also perform inherent accumulator-to-accumulator operations that require no additional data. these instructions are add , sub and neg . the dsp engine has options selected through bits in the cpu core control register (corcon), as listed below: fractional or integer dsp multiply (if) signed or unsigned dsp multiply (us) conventional or convergent rounding (rnd) automatic saturation on/off for acca (sata) automatic saturation on/off for accb (satb) automatic saturation on/off for writes to data memory (satdw) accumulator saturation mode selection (accsat) a block diagram of the dsp engine is shown in figure 3-3 . table 3-1: dsp instructions summary instruction algebraic operation acc write back clr a = 0 yes ed a = (x ? y) 2 no edac a = a + (x ? y) 2 no mac a = a + (x * y) yes mac a = a + x 2 no movsac no change in a yes mpy a = x * y no mpy a = x 2 no mpy.n a = ? x * y no msc a = a ? x * y yes downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 39 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 3-3: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to/from w array adder negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 saturate multiplier/scaler 17-bit downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 40 ? 2008-2014 microchip technology inc. 3.6.1 multiplier the 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. unsigned operands are zero-extended into the 17th bit of the multiplier input value. signed operands are sign-extended into the 17th bit of the multiplier input value. the output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. integer data is inherently represented as a signed 2s complement value, where the most significant bit (msb) is defined as a sign bit. the range of an n-bit 2s complement integer is -2 n-1 to 2 n-1 C 1. for a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7fff), including 0. for a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7fff ffff). when the multiplier is configured for fractional multiplication, the data is represented as a 2s complement fraction, where the msb is defined as a sign bit and the radix point is implied to lie just after the sign bit (qx format). the range of an n-bit 2s complement fraction with this implied radix point is -1.0 to (1 C 2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 (0x8000) to 0.999969482 (0x7fff) including 0 and has a precision of 3.01518x10 -5 . in fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10 -10 . the same multiplier is used to support the mcu multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. the mul instruction can be directed to use byte or word-sized operands. byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the w array. 3.6.2 data accumulators and adder/subtracter the data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. it can select one of two accumulators (a or b) as its pre- accumulation source and post-accumulation destination. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.6.2.1 adder/subtracter, overflow and saturation the adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. in the case of addition, the carry/b orrow input is active-high and the other input is true data (not complemented). in the case of subtraction, the carry/borrow input is active-low and the other input is complemented. the adder/subtracter generates overflow status bits, sa/sb and oa/ob, which are latched and reflected in the status register: overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. overflow into guard bits, 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits are not identical to each other. the adder has an additional saturation block that controls accumulator data saturation, if selected. it uses the result of the adder, the overflow status bits described previously and the sat ? 2008-2014 microchip technology inc. ds70000318g-page 41 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 the sa and sb bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. when set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). when saturation is not enabled, sa and sb default to bit 39 overflow and thus, indicate that a cata- strophic overflow has occurred. if the covte bit in the intcon1 register is set, sa and sb bits will generate an arithmetic warning trap when saturation is disabled. the overflow and saturation status bits can optionally be viewed in the status register (sr) as the logical or of oa and ob (in bit oab) and the logical or of sa and sb (in bit sab). programmers can check one bit in the status register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. this is useful for complex number arithmetic, which typically uses both accumulators. the device supports three saturation and overflow modes: bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7fffffffff) or maximally negative 9.31 value (0x8000000000) into the target accumu- lator. the sa or sb bit is set and remains set until cleared by the user application. this condition is referred to as super saturation and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007fffffff) or maximally nega- tive 1.31 value (0x0080000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. when this saturation mode is in effect, the guard bits are not used, so the oa, ob or oab bits are never set. bit 39 catastrophic overflow: the bit 39 overflow status bit from the adder is used to set the sa or sb bit, which remains set until cleared by the user application. no saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 3.6.3 accumulator write back the mac class of instructions (with the exception of mpy , mpy.n , ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: w13, register direct: the rounded contents of the non-target accumulator are written into w13 as a 1.15 fraction. [w13] + = 2, register indirect with post-increment: the rounded contents of the non-target accumulator are written into the address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 3.6.3.1 round logic the round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. if rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. conventional rounding zero-extends bit 15 of the accu- mulator and adds it to the accxh word (bits 16 through 31 of the accumulator). if the accxl word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xffff (0x8000 included), accxh is incremented. if accxl is between 0x0000 and 0x7fff, accxh is left unchanged. a consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when accxl equals 0x8000. in this case, the least significant bit (bit 16 of the accumulator) of accxh is examined: if it is 1 , accxh is incremented. if it is 0 , accxh is not modified. assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 42 ? 2008-2014 microchip technology inc. the sac and sac.r instructions store either a truncated ( sac ), or rounded ( sac.r ) version of the contents of the target accumulator to data memory via the x bus, subject to data saturation (see section 3.6.3.2 data space write saturation ). for the mac class of instructions, the accumulator write- back operation functions in the same manner, addressing combined mcu (x and y) data space though the x bus. for this class of instructions, the data is always subject to rounding. 3.6.3.2 data space write saturation in addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. the data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. these inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: for input data greater than 0x007fff, data written to memory is forced to the maximum positive 1.15 value, 0x7fff. for input data less than 0xff8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. the most significant bit of the source (bit 39) is used to determine the sign of the operand being tested. if the satdw bit in the corcon register is not set, the input data is always passed through unmodified under all conditions. 3.6.4 barrel shifter the barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. the source can be either of the two dsp accumulators or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value shifts the operand right. a negative value shifts the operand left. a value of 0 does not modify the operand. the barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for dsp shift operations and a 16-bit result for mcu shift operations. data from the x bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 43 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 4.0 memory organization the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 architecture features separate program and data memory spaces and buses. this architecture also allows the direct access to program memory from the data space during code execution. 4.1 program address space the program address memory space of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit program counter (pc) during program execution, or from table operation or data space remapping, as described in section 4.6 interfacing program and data memory spaces . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. the memory maps for the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices are shown in figure 4-1 . figure 4-1: program memory maps for dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices note: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to program memory (ds70202) in the dspic33f/pic24h family reference man- ual? , which is available from the microchip web site ( www.microchip.com ). reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x001000 0x000ffe (1792 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read 0 s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table dspic33fj06gs101/102/202 configuration memory space user memory space reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x002c00 0x002bfe (5376 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 0xf7fffe unimplemented (read 0 s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table dspic33fj16gs402/404/502/504 configuration memory space user memory space reserved 0xff0002 devid (2) reserved 0xfefffe 0xff0000 0xfffffe 0xff0002 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 44 ? 2008-2014 microchip technology inc. 4.1.1 program memory organization the program memory space is organized in word- addressable blocks. although it is treated as 24 bits wide, it is more appropriate consider each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address (see figure 4-2 ). program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during the code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 4.1.2 interrupt and trap vectors all dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000ff and 0x000100 to 0x0001ff. these vector tables allow each of the device interrupt sources to be handled by separate interrupt service routines (isrs). a more detailed discussion of the interrupt vector tables is provided in section 7.1 interrupt vector table . figure 4-2: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 0000000000000000 00000000 00000000 program memory phantom byte (read as 0 ) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 45 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 4.2 data address space the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 cpu has a separate, 16-bit-wide data memory space. the data space is accessed using separate address generation units (agus) for read and write operations. the data memory maps is shown in figure 4-3 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this arrangement gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility area (see section 4.6.3 reading data from program memory using program space visibility ). dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices implement up to 2 kbytes of data memory. should an ea point to a location outside of this area, an all zero word or byte will be returned. 4.2.1 data space width the data memory space is organized in byte addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] that results in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. data byte writes only write to the corresponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the error occurred on a read, the instruction underway is completed. if the error occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the least significant byte. the most significant byte is not modified. a sign-extend ( se ) instruction is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. 4.2.3 sfr space the first 2 kbytes of the near data space, from 0x0000 to 0x07ff, is primarily occupied by special function registers (sfrs). these are used by the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 core and peripheral modules for controlling the operation of the device. sfrs are distributed among the modules that they control, and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as 0 . 4.2.4 near data space the 8-kbyte area, between 0x0000 and 0x1fff, is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing mode with a 16-bit address field or by using indirect addressing mode using a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams for device-specific information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 46 ? 2008-2014 microchip technology inc. figure 4-3: data memory map for dspic3 3fj06gs101/102 devices with 256 bytes of ram 0x0000 0x07fe 0x08fe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x0900 2-kbyte sfr space 256 bytes sram space 0x8001 0x8000 x data unimplemented (x) 0x087e 0x0880 0x087f 0x0881 0x08ff 0x0901 0x1fff 0x1ffe 0x2001 0x2000 8-kbyte near data space sfr space x data ram (x) y data ram (y) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 47 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 4-4: data memory map for dspic3 3fj06gs202 device with 1-kbyte ram 0x0000 0x07fe 0x0bfe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x0c00 2-kbyte sfr space 1-kbyte sram space 0x8001 0x8000 sfr space x data unimplemented (x) 0x09fe 0x0a00 0x09ff 0x0a01 0x0bff 0x0c01 0x1fff 0x1ffe 0x2001 0x2000 8-kbyte near data space x data ram (x) y data ram (y) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 48 ? 2008-2014 microchip technology inc. figure 4-5: data memory map for dspic33fj16gs402/404/502/504 devices with 2-kbyte ram 0x0000 0x07fe 0x0ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x1000 2-kbyte sfr space 2-kbyte sram space 0x8001 0x8000 sfr space x data unimplemented (x) 0x0bfe 0x0c00 0x0bff 0x0c01 0x0fff 0x1001 0x1fff 0x1ffe 0x2001 0x2000 8-kbyte near data space y data ram (y) x data ram (x) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 49 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 4.2.5 x and y data spaces the core has two data spaces, x and y. these data spaces can be considered either separate (for some dsp instructions), or as one unified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. this feature allows certain instructions to concurrently fetch two words from ram, thereby enabling efficient execution of dsp algorithms, such as finite impulse response (fir) filtering and fast fourier transform (fft). the x data space is used by all instructions and supports all addressing modes. x data space has separate read and write data buses. the x read data bus is the read data path for all instructions that view data space as combined x and y address space. it is also the x data prefetch path for the dual operand dsp instructions ( mac class). the y data space is used in concert with the x data space by the mac class of instructions ( clr , ed , edac , mac , movsac , mpy , mpy.n and msc ) to provide two concurrent data read paths. both the x and y data spaces support modulo addressing mode for all instructions, subject to addressing mode restrictions. bit-reversed addressing mode is only supported for writes to x data space. all data memory writes, including in dsp instructions, view data space as combined x and y address space. the boundary between the x and y data spaces is device-dependent and is not user-programmable. all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes, or 32k words, though the implemented memory locations vary by device. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 50 ? 2008-2014 microchip technology inc. table 4-1: cpu core register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 working register 0 0000 wreg1 0002 working register 1 0000 wreg2 0004 working register 2 0000 wreg3 0006 working register 3 0000 wreg4 0008 working register 4 0000 wreg5 000a working register 5 0000 wreg6 000c working register 6 0000 wreg7 000e working register 7 0000 wreg8 0010 working register 8 0000 wreg9 0012 working register 9 0000 wreg10 0014 working register 10 0000 wreg11 0016 working register 11 0000 wreg12 0018 working register 12 0000 wreg13 001a working register 13 0000 wreg14 001c working register 14 0000 wreg15 001e working register 15 0800 splim 0020 stack pointer limit register xxxx accal 0022 accal xxxx accah 0024 accah xxxx accau 0026 acca<39> acca<39> acca<39> acca<39> acca<39> acca<39> acca<39> acca<39> accau xxxx accbl 0028 accbl xxxx accbh 002a accbh xxxx accbu 002c accb<39> accb<39> a ccb<39> accb<39> accb<39> accb <39> accb<39> accb<39> accbu xxxx pcl 002e program counter low word register 0000 pch 0030 program counter high byte register 0000 tblpag 0032 table page address pointer register 0000 psvpag 0034 program memory visibility page address pointer register 0000 rcount 0036 repeat loop counter register xxxx dcount 0038 dcount<15:0> xxxx dostartl 003a dostartl<15:1> 0x x x x dostarth 003c d o s t a r t h < 5 : 0 > 00xx doendl 003e doendl<15:1> 0x x x x doendh 0040 doendh 00xx sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 us edt dl2 dl1 dl0 sata satb satdw accsat ipl3 psv rnd if 0020 modcon 0046 xmoden ymoden bwm3 bwm2 bwm1 bwm0 ywm3 ywm2 ywm1 ywm0 xwm3 xwm2 xwm1 xwm0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 51 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-2: change notificat ion register map for ds pic33fj06gs101 table 4-3: change notification register map for dspic33fj06gs102, dspic33fj06gs202, dspic33fj16gs402 and dspic33fj16gs502 table 4-4: change notification re gister map for dspic33fj1 6gs404 and dspic33fj16gs504 xmodsrt 0048 xs<15:1> 0x x x x xmodend 004a xe<15:1> 1x x x x ymodsrt 004c ys<15:1> 0x x x x ymodend 004e ye<15:1> 1x x x x xbrev 0050 bren xb14 xb13 xb12 xb11 xb10 xb9 xb8 xb7 xb6 xb5 xb4 xb3 xb2 xb1 xb0 xxxx disicnt 0052 disable interrupts counter register xxxx table 4-1: cpu core register map (continued) file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnpu1 0068 cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a l l resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie cn7ie cn6ie cn5ie cn4ie c n3ie cn2ie cn1ie cn0ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pu e cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 cn29ie cn28ie cn27ie cn26ie cn25ie cn24ie cn23ie cn22ie cn21ie cn20ie cn19ie cn18ie cn 17ie cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue cn7pu e cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a cn29pue cn28pue cn27pue cn26pue cn25pue cn24pue cn23pue cn22pue cn21pue cn20pue cn19pue cn18pue cn17pue cn16pue 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 52 ? 2008-2014 microchip technology inc. table 4-5: interrupt controller register map for dspic33fj06gs101 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 adif u1txif u1rxif spi1if spi1eif t 2 i f t 1 i fo c 1 i f i n t 0 i f 0000 ifs1 0086 i n t 2 i f i n t 1 i fc n i f m i 2 c 1 i fs i 2 c 1 i f 0000 ifs3 008a psemif 0000 ifs4 008c u 1 e i f 0000 ifs5 008e p w m 1 i f 0000 ifs6 0090 adcp1if adcp0if p w m 4 i f 0000 ifs7 0092 adcp3if 0000 iec0 0094 adie u1txie u1rxie spi1ie spi1eie t 2 i e t 1 i eo c 1 i e i n t 0 i e 0000 iec1 0096 i n t 2 i e int1ie cnie mi2c1ie si2c1ie 0000 iec2 0098 0000 iec3 009a p s e m i e 0000 iec4 009c u 1 e i e 0000 iec5 009e p w m 1 i e 0000 iec6 00a0 adcp1ie adcp0ie p w m 4 i e 0000 iec7 00a2 adcp3ie 0000 ipc0 00a4 t1ip2 t1ip1 t1ip0 oc1ip2 oc1ip1 oc1ip0 int0ip2 int0ip1 int0ip2 4404 ipc1 00a6 t2ip2 t2ip1 t2ip0 4000 ipc2 00a8 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 4440 ipc3 00aa - adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 0044 ipc4 00ac cnip2 cnip1 cnip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4044 ipc5 00ae int1ip2 int1ip21 int1ip0 0004 ipc7 00b2 int2ip2 int2ip1 int2ip0 0040 ipc14 00c0 psemip2 psemip1 psemip0 0040 ipc16 00c4 u1eip2 u1eip1 u1eip0 0400 ipc23 00d2 pwm1ip2 pwm1ip1 pwm1ip0 0040 ipc24 00d4 pwm4ip2 pwm4ip1 pwm4ip0 4400 ipc27 00da adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 0040 ipc28 00dc adcp3ip2 adcp3ip1 adcp3ip0 0000 inttreg 00e0 ilr3 ilr2 ilr1 ilr0 vecnum6 vecnum5 vecnum4 ve cnum3 vecnum2 vecnum1 vecnum0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 53 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-6: interrupt controller register map for dspic33fj06gs102 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 adif u1txif u1rxif spi1if spi1eif t 2 i f t 1 i fo c 1 i f i n t 0 i f 0000 ifs1 0086 i n t 2 i f int1if cnif m i 2 c 1 i fs i 2 c 1 i f 0000 ifs3 008a p s e m i f 0000 ifs4 008c u 1 e i f 0000 ifs5 008e pwm2if pwm1if 0000 ifs6 0090 adcp1if adcp0if 0000 ifs7 0092 adcp2if 0000 iec0 0094 adie u1txie u1rxie spi1ie spi1eie t 2 i e t 1 i eo c 1 i e i n t 0 i e 0000 iec1 0096 i n t 2 i e int1ie cnie mi2c1ie si2c1ie 0000 iec3 009a psemie 0000 iec4 009c u 1 e i e 0000 iec5 009e pwm2ie pwm1ie 0000 iec6 00a0 adcp1ie adcp0ie 0000 iec7 00a2 adcp2ie 0000 ipc0 00a4 t 1 i p 2t 1 i p 1t 1 i p 0 oc1ip2 oc1ip1 oc1ip0 int0ip2 int0ip1 int0ip0 4404 ipc1 00a6 t 2 i p 2t 2 i p 1t 2 i p 0 4000 ipc2 00a8 u1rxip2 u1rxip2 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 4440 ipc3 00aa - adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 0044 ipc4 00ac cnip2 cnip1 cnip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4044 ipc5 00ae int1ip2 int1ip1 int1ip0 0004 ipc7 00b2 int2ip2 int2ip1 int2ip0 0040 ipc14 00c0 psemip2 psemip1 psemip0 0040 ipc16 00c4 u1eip2 u1eip1 u1eip0 0040 ipc23 00d2 pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 4400 ipc27 00da adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 4400 ipc28 00dc adcp2ip2 adcp2ip1 adcp2ip0 0004 inttreg 00e0 ilr3 ilr2 ilr1 ilr0 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 54 ? 2008-2014 microchip technology inc. table 4-7: interrupt controller register map for dspic33fj06g202 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 adif u1txif u1rxif spi1if spi1eif t 2 i f t1if oc1if ic1if int0if 0000 ifs1 0086 i n t 2 i f int1if cnif ac1if mi2c1if si2c1if 0000 ifs3 008a psemif 0000 ifs4 008c u 1 e i f 0000 ifs5 008e pwm2if pwm1if 0000 ifs6 0090 adcp1if adcp0if a c 2 i f 0000 ifs7 0092 adcp6if adcp2if 0000 iec0 0094 adie u1txie u1rxie spi1ie spi1eie t 2 i e t1ie oc1ie ic1ie int0ie 0000 iec1 0096 i n t 2 i e int1ie cnie ac1ie mi2c1ie si2c1ie 0000 iec3 009a p s e m i e 0000 iec4 009c u 1 e i e 0000 iec5 009e pwm2ie pwm1ie 0000 iec6 00a0 adcp1ie adcp0ie a c 2 i e 0000 iec7 00a2 adcp6ie adcp2ie 0000 ipc0 00a4 t 1 i p 2t 1 i p 1t 1 i p 0 oc1ip2 oc1ip1 oc1ip0 ic1ip2 ic1ip1 ic1ip0 int0ip2 int0ip1 int0ip0 4444 ipc1 00a6 t 2 i p 2t 2 i p 1t 2 i p 0 4000 ipc2 00a8 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 4440 ipc3 00aa - adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 0044 ipc4 00ac cnip2 cnip1 cnip0 ac1ip2 ac1ip1 ac1ip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4444 ipc5 00ae int1ip2 int1ip1 int1ip0 0004 ipc7 00b2 int2ip2 int2ip1 int2ip0 0040 ipc14 00c0 psemip2 psemip1 psemip0 0040 ipc16 00c4 u1eip2 u1eip1 u1eip0 0040 ipc23 00d2 pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 4400 ipc25 00d6 ac2ip2 ac2ip1 ac2ip0 4000 ipc27 00da adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 4400 ipc28 00dc adcp2ip2 adcp2ip1 adcp2ip0 0004 ipc29 00de adcp6ip2 adcp6ip1 adcp6ip0 0004 inttreg 00e0 ilr3 ilr2 ilr1 ilr0 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 55 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-8: interrupt controller register map for dspic33fj16gs402/404 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 adif u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 ifs1 0086 i n t 2 i f int1if cnif mi2c1if si2c1if 0000 ifs3 008a psemif 0000 ifs4 008c u 1 e i f 0000 ifs5 008e pwm2if pwm1if 0000 ifs6 0090 adcp1if adcp0if p w m 3 i f 0000 ifs7 0092 adcp3if adcp2if 0000 iec0 0094 adie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 iec1 0096 i n t 2 i e int1ie cnie m i 2 c 1 i es i 2 c 1 i e 0000 iec3 009a psemie 0000 iec4 009c u 1 e i e 0000 iec5 009e pwm2ie pwm1ie 0000 iec6 00a0 adcp1ie adcp0ie p w m 3 i e 0000 iec7 00a2 adcp3ie adcp2ie 0000 ipc0 00a4 t1ip2 t1ip1 t1ip0 oc1ip2 oc1ip1 oc1ip0 ic1ip2 ic1ip1 ic1ip0 int0ip2 int0ip1 int0ip2 4444 ipc1 00a6 t2ip2 t2ip1 t2ip0 oc2ip2 oc2ip1 oc2ip0 ic2ip2 ic2ip1 ic2ip0 4440 ipc2 00a8 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 t 3 i p 2t 3 i p 1t 3 i p 0 4444 ipc3 00aa - adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 0044 ipc4 00ac cnip2 cnip1 cnip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4044 ipc5 00ae int1ip2 int1ip1 int1ip0 0004 ipc7 00b2 int2ip2 int2ip1 int2ip0 0040 ipc14 00c0 psemip2 psemip1 psemip0 0040 ipc16 00c4 u1eip2u1eip1u1eip0 0040 ipc23 00d2 pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 - 4400 ipc24 00d4 pwm3ip2 pwm3ip1 pwm3ip0 0004 ipc27 00da adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 - 4400 ipc28 00dc adcp3ip2 adcp3ip1 adcp3ip0 adcp2ip2 adcp2ip1 adcp2ip0 0044 inttreg 00e0 ilr3 ilr2 ilr1 ilr0 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 56 ? 2008-2014 microchip technology inc. table 4-9: interrupt controller register map for dspic33fj16gs502 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0 err matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 adif u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 ifs1 0086 i n t 2 i f int1if cnif ac1if mi2c1if si2c1if 0000 ifs3 008a psemif 0000 ifs4 008c u 1 e i f 0000 ifs5 008e pwm2if pwm1if 0000 ifs6 0090 adcp1if adcp0if ac4if ac3if ac2if pwm4if pwm3if 0000 ifs7 0092 adcp6if adcp3if adcp2if 0000 iec0 0094 adie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 iec1 0096 i n t 2 i e int1ie cnie ac1ie mi2c1ie si2c1ie 0000 iec3 009a psemie 0000 iec4 009c u 1 e i e 0000 iec5 009e pwm2ie pwm1ie 0000 iec6 00a0 adcp1ie adcp0ie ac4ie ac3ie ac2ie pwm4ie pwm3ie 0000 iec7 00a2 adcp6ie adcp3ie adcp2ie 0000 ipc0 00a4 t1ip2 t1ip1 t1ip0 oc1ip2 oc1ip1 oc1ip0 ic1ip2 ic1ip1 ic1ip0 int0ip2 int0ip1 int0ip2 4444 ipc1 00a6 t2ip2 t2ip1 t2ip0 oc2ip2 oc2ip1 oc2ip0 ic2ip2 ic2ip1 ic2ip0 - 4440 ipc2 00a8 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 t3ip2 t3ip1 t3ip0 4444 ipc3 00aa - - adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 0044 ipc4 00ac cnip2 cnip1 cnip0 ac1ip2 ac1ip1 ac1ip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4444 ipc5 00ae int1ip2 int1ip1 int1ip0 0004 ipc7 00b2 int2ip2 int2ip1 int2ip0 0040 ipc14 00c0 psemip2 psemip1 psemip0 0040 ipc16 00c4 u1eip2 u1eip1 u1eip0 0040 ipc23 00d2 pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 4400 ipc24 00d4 pwm4ip2 pwm4ip1 pwm4ip0 pwm3ip2 pwm3ip1 pwm3ip0 0044 ipc25 00d6 ac2ip2 ac2ip1 ac2ip0 4000 ipc26 00d8 ac4ip2 ac4ip1 ac4ip0 ac3ip2 ac3ip1 ac3ip0 0044 ipc27 00da adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 - 4400 ipc28 00dc adcp3ip2 adcp3ip1 adcp3ip0 adcp2ip2 adcp2ip1 adcp2ip0 0044 ipc29 00de adcp6ip2 adcp6ip1 adcp6ip0 0004 inttreg 00e0 ilr3 ilr2 ilr1 ilr0 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 57 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-10: interrupt controller register map for dspic33fj16gs504 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 adif u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 ifs1 0086 i n t 2 i f int1if cnif ac1if mi2c1if si2c1if 0000 ifs3 008a p s e m i f 0000 ifs4 008c u 1 e i f 0000 ifs5 008e pwm2if pwm1if 0000 ifs6 0090 adcp1if adcp0if ac4if ac3if ac2if pwm4if pwm3if 0000 ifs7 0092 adcp6if adcp5if adcp4if adcp3if adcp2if 0000 iec0 0094 adie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 iec1 0096 i n t 2 i e int1ie cnie ac1ie mi2c1ie si2c1ie 0000 iec3 009a psemie 0000 iec4 009c u 1 e i e 0000 iec5 009e pwm2ie pwm1ie 0000 iec6 00a0 adcp1ie adcp0ie ac4ie ac3ie ac2ie pwm4ie pwm3ie 0000 iec7 00a2 adcp6ie adcp5ie adcp 4ie adcp3ie adcp2ie 0000 ipc0 00a4 t1ip2 t1ip1 t1ip0 oc1ip2 oc1ip1 oc1ip0 ic1ip2 ic1ip1 ic1ip0 int0ip2 int0ip1 int0ip2 4444 ipc1 00a6 t2ip2 t2ip1 t2ip0 oc2ip2 oc2ip1 oc2ip0 ic2ip2 ic2ip1 ic2ip0 4440 ipc2 00a8 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 t3ip2 t3ip1 t3ip0 4444 ipc3 00aa - adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 0044 ipc4 00ac cnip2 cnip1 cnip0 ac1ip2 ac1ip1 ac1ip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4444 ipc5 00ae int1ip2 int1ip1 int1ip0 0004 ipc7 00b2 i n t 2 i p 2i n t 2 i p 1i n t 2 i p 0 0040 ipc14 00c0 psemip2 psemip1 psemip0 0040 ipc16 00c4 u1eip2 u1eip1 u1eip0 0040 ipc23 00d2 pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 4400 ipc24 00d4 pwm4ip2 pwm4ip1 pwm4ip0 pwm3ip2 pwm3ip1 pwm3ip0 0044 ipc25 00d6 ac2ip2 ac2ip1 ac2ip0 4000 ipc26 00d8 ac4ip2 ac4ip1 ac4ip0 ac3ip2 ac3ip1 ac3ip0 0440 ipc27 00da adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 4400 ipc28 00dc adcp5ip2 adcp5ip1 adcp5ip0 adcp4ip2 adcp4ip1 adcp4ip0 adcp3ip2 adcp3ip1 adcp3ip0 adcp2ip2 adcp2ip1 adcp2ip0 4444 ipc29 00de adcp6ip2 adcp6ip1 adcp6ip0 0004 inttreg 00e0 ilr3 ilr2 ilr1 ilr0 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 58 ? 2008-2014 microchip technology inc. table 4-11: timer register map for dspic33fj06gs101 and dspic33fj06gsx02 table 4-12: timer register map for dspic33fj16gsx02 and dspic33fj16gsx04 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 period register 1 ffff t1con 0104 ton t s i d l tgate tckps1 tckps0 tsync tcs 0000 tmr2 0106 timer2 register 0000 pr2 010c period register 2 ffff t2con 0110 ton t s i d l tgate tckps1 tckps0 t c s 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 period register 1 ffff t1con 0104 ton t s i d l tgate tckps1 tckps0 tsync tcs 0000 tmr2 0106 timer2 register 0000 tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register 0000 pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton t s i d l tgate tckps1 tckps0 t32 t c s 0000 t3con 0112 ton t s i d l tgate tckps1 tckps0 t c s 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-13: input capture regi ster map for dspic33fj06gs202 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input capture 1 register xxxx ic1con 0142 i c s i d l ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 59 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-14: input capture register map fo r dspic33fj16gsx02 and dspic33fj16gsx04 table 4-16: output compare register map for dspic33fj16gsx02 and dspic33fj06gsx04 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input capture 1 register xxxx ic1con 0142 i c s i d l ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic2buf 0144 input capture 2 register xxxx ic2con 0146 i c s i d l ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-15: output compare register map for dspic33fj06gs101 and dspic33fj06gsx02 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register xxxx oc1r 0182 output compare 1 register xxxx oc1con 0184 o c s i d l ocflt octsel ocm2 ocm1 ocm0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register xxxx oc1r 0182 output compare 1 register xxxx oc1con 0184 o c s i d l ocflt octsel ocm2 ocm1 ocm0 0000 oc2rs 0186 output compare 2 secondary register xxxx oc2r 0188 output compare 2 register xxxxx oc2con 018a o c s i d l ocflt octsel ocm2 ocm1 ocm0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-17: high-speed pwm register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ptcon 0400 pten ptsidl sestat seien eipu syncpol syncoen syncen syncsrc1 syncsrc0 sevtps3 sevtps2 sevtps1 sevtps0 0000 ptcon2 0402 pclkdiv2 pclkdiv1 pclkdiv0 0000 ptper 0404 ptper<15:0> fff8 sevtcmp 0406 sevtcmp<15:3> 0000 mdc 040a mdc<15:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 60 ? 2008-2014 microchip technology inc. table 4-18: high-speed pwm generator 1 register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon1 0420 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dtc0 cam xpres iue 0000 iocon1 0422 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltda t1 fltdat0 cldat1 cldat0 swap osync 0000 fclcon1 0424 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 flt src1 fltsrc0 fltpol fltmod1 fltmod0 0000 pdc1 0426 pdc1<15:0> 0000 phase1 0428 phase1<15:0> 0000 dtr1 042a dtr1<13:0> 0000 altdtr1 042c altdtr1<13:0> 0000 sdc1 042e sdc1<15:0> 0000 sphase1 0430 sphase1<15:0> 0000 trig1 0432 trgcmp<15:3> 0000 trgcon1 0434 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 0000 strig1 0436 strgcmp<15:3> 0000 pwmcap1 0438 pwmcap1<15:3> 0000 lebcon1 043a phr phf plr plf fltleben clleben leb6 leb5 leb4 leb3 leb2 leb 1 leb0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-19: high-speed pwm generator 2 register map for dspic33fj06gs102/202 and dspic33fj16gsx02/x04 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets pwmcon2 0440 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dt c0 cam xpres iue 0000 iocon2 0442 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 f ltdat0 cldat1 cldat0 swap osync 0000 fclcon2 0444 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 fltmod0 0000 pdc2 0446 pdc2<15:0> 0000 phase2 0448 phase2<15:0> 0000 dtr2 044a dtr2<13:0> 0000 altdtr2 044c altdtr2<13:0> 0000 sdc2 044e sdc2<15:0> 0000 sphase2 0450 sphase2<15:0> 0000 trig2 0452 trgcmp<15:3> 0000 trgcon2 0454 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 t rgstrt2 trgstrt1 trgstrt0 0000 strig2 0456 strgcmp<15:3> 0000 pwmcap2 0458 pwmcap2<15:3> 0000 lebcon2 045a phr phf plr plf fltleben clleben leb6 leb5 leb4 leb3 leb2 leb1 leb 0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 61 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-20: high-speed pwm generator 3 register map for dspic33fj16gsx02/x04 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 bit 0 all resets pwmcon3 0460 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dt c0 cam xpres iue 0000 iocon3 0462 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 f ltdat0 cldat1 cldat0 swap osync 0000 fclcon3 0464 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 fltmod0 0000 pdc3 0466 pdc3<15:0> 0000 phase3 0468 phase3<15:0> 0000 dtr3 046c dtr3<13:0> 0000 altdtr3 046c altdtr3<13:0> 0000 sdc3 046e sdc3<15:0> 0000 sphase3 0470 sphase3<15:0> 0000 trig3 0472 trgcmp<15:3> 0000 trgcon3 0474 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 t rgstrt2 trgstrt1 trgstrt0 0000 strig3 0476 strgcmp<15:3> 0000 pwmcap3 0478 pwmcap3<15:3> 0000 lebcon3 047a phr phf plr plf fltleben clleben leb6 leb5 leb4 leb3 leb2 leb1 leb 0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-21: high-speed pwm generator 4 register map for dspic33fj06gs101 and dspic33fj16g s50x devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets pwmcon4 0480 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dt c0 cam xpres iue 0000 iocon4 0482 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 f ltdat0 cldat1 cldat0 swap osync 0000 fclcon4 0484 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 fltmod0 0000 pdc4 0486 pdc4<15:0> 0000 phase4 0488 phase4<15:0> 0000 dtr4 048a dtr4<13:0> 0000 altdtr4 048a altdtr4<13:0> 0000 sdc4 048e sdc4<15:0> 0000 sphase4 0490 sphase4<15:0> 0000 trig4 0492 trgcmp<15:3> 0000 trgcon4 0494 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 t rgstrt2 trgstrt1 trgstrt0 0000 strig4 0496 strgcmp<15:3> 0000 pwmcap4 0498 pwmcap4<15:3> 0000 lebcon4 049a phr phf plr plf fltleben clleben leb6 leb5 leb4 leb3 leb2 leb1 leb 0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 62 ? 2008-2014 microchip technology inc. table 4-23: uart1 register map table 4-24: spi1 register map table 4-22: i2c1 register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 i2c1 receive register 0000 i2c1trn 0202 i2c1 transmit register 00ff i2c1brg 0204 baud rate generator register 0000 i2c1con 0206 i2cen i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 020a i2c1 address register 0000 i2c1msk 020c amsk<9:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten usidl iren rtsmd uen1 uen0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u1txreg 0224 uart1 transmit register xxxx u1rxreg 0226 uart1 receive register 0000 u1brg 0228 baud rate generator prescaler 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien spisidl spirov spitbf spirbf 0000 spi1con1 0242 dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi1con2 0244 frmen spifsd frmpol frmdly 0000 spi1buf 0248 spi1 transmit and receive buffer register 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 63 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-25: high-speed 10-bit adc register map for dspic33fj06gs101 devices only table 4-26: high-speed 10-bit adc register map for dspic33fj06gs102 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets adcon 0300 adon adsidl slowclk g s w t r g form eie order seqsamp asyncsamp adcs2 adcs1 adcs0 0003 adpcfg 0302 p c f g 7p c f g 6 pcfg3 pcfg2 pcfg1 pcfg0 0000 adstat 0306 p3rdy p1rdy p0rdy 0000 adbase 0308 adbase<15:1> 0000 adcpc0 030a irqen1 pend1 swtrg1 trgsrc14 trgsrc13 t rgsrc12 trgsrc11 trgsrc10 irqen0 pend0 swtrg0 trgsrc04 trgsrc03 trgs rc02 trgsrc01 trgsrc00 0000 adcpc1 030c irqen3 pend3 swtrg3 trgsrc34 trgsrc33 trgsrc32 trgsrc31 trgsrc30 0000 adcbuf0 0320 adc data buffer 0 xxxx adcbuf1 0322 adc data buffer 1 xxxx adcbuf2 0324 adc data buffer 2 xxxx adcbuf3 0326 adc data buffer 3 xxxx adcbuf6 032c adc data buffer 6 xxxx adcbuf7 032e adc data buffer 7 xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 bit 0 all resets adcon 0300 adon adsidl slowclk g s w t r g form eie order seqsamp asyncsamp adcs2 adcs1 adcs0 0003 adpcfg 0302 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 adstat 0306 p2rdy p1rdy p0rdy 0000 adbase 0308 adbase<15:1> 0000 adcpc0 030a irqen1 pend1 swtrg1 trgsrc1 4 trgsrc13 trgsrc12 trgsrc11 trgs rc10 irqen0 pend0 swtrg0 trgsrc04 tr gsrc03 trgsrc02 trgsrc01 trgsrc00 0000 adcpc1 030c irqen2 pend2 swtrg2 trgsrc24 trgs rc23 trgsrc22 trgsrc21 trgsrc20 0000 adcbuf0 0320 adc data buffer 0 xxxx adcbuf1 0322 adc data buffer 1 xxxx adcbuf2 0324 adc data buffer 2 xxxx adcbuf3 0326 adc data buffer 3 xxxx adcbuf4 0328 adc data buffer 4 xxxx adcbuf5 032a adc data buffer 5 xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 64 ? 2008-2014 microchip technology inc. table 4-27: high-speed 10-bit adc register map for dspic33fj06gs202 devices only table 4-28: high-speed 10-bit adc register map for dspic33fj16gs402/404 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets adcon 0300 adon adsidlslowclk g s w t r g form eie order seqsamp asyncsamp adcs2 adcs1 adcs0 0003 adpcfg 0302 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 adstat 0306 p6rdy p2rdy p1rdy p0rdy 0000 adbase 0308 adbase<15:1> 0000 adcpc0 030a irqen1 pend1 swtrg1 trgsrc14 trgsrc13 trgsrc12 trgsrc11 t rgsrc10 irqen0 pend0 swtrg0 trgsrc04 t rgsrc03 trgsrc02 t rgsrc01 trgsrc00 0000 adcpc1 030c irqen2 pend2 swtrg2 trgsrc24 trgs rc23 trgsrc22 trg src21 trgsrc20 0000 adcpc3 0310 irqen6 pend6 swtrg6 trgsrc64 trgs rc63 trgsrc62 trg src61 trgsrc60 0000 adcbuf0 0320 adc data buffer 0 xxxx adcbuf1 0322 adc data buffer 1 xxxx adcbuf2 0324 adc data buffer 2 xxxx adcbuf3 0326 adc data buffer 3 xxxx adcbuf4 0328 adc data buffer 4 xxxx adcbuf5 032a adc data buffer 5 xxxx adcbuf12 0338 adc data buffer 12 xxxx adcbuf13 033a adc data buffer13 xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adcon 0300 adon adsidlslowclk g s w t r g form eie order seqsamp asyncsamp adcs2 adcs1 adcs0 0003 adpcfg 0302 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 adstat 0306 p3rdy p2rdy p1rdy p0rdy 0000 adbase 0308 adbase<15:1> 0000 adcpc0 030a irqen1 pend1 swtrg1 trgsrc 14 trgsrc13 trgsrc12 trgsrc11 trgs rc10 irqen0 pend0 swtrg0 trgsrc04 trg src03 trgsrc02 trgsrc01 trgsrc00 0000 adcpc1 030c irqen3 pend3 swtrg3 trgsrc34 trgsrc33 trgsrc32 trgsrc31 t rgsrc30 irqen2 pend2 swtrg2 trgsrc24 t rgsrc23 trgsrc22 trgsrc21 trgsrc20 0000 adcbuf0 0320 adc data buffer 0 xxxx adcbuf1 0322 adc data buffer 1 xxxx adcbuf2 0324 adc data buffer 2 xxxx adcbuf3 0326 adc data buffer 3 xxxx adcbuf4 0328 adc data buffer 4 xxxx adcbuf5 032a adc data buffer 5 xxxx adcbuf6 032c adc data buffer 6 xxxx adcbuf7 032e adc data buffer 7 xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 65 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-29: high-speed 10-bit adc register map for dspic33fj16gs502 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adcon 0300 adon adsidl slowclk g s w t r g form eie order seqsamp asyncsamp adcs2 adcs1 adcs0 0003 adpcfg 0302 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 adstat 0306 p6rdy p3rdy p2rdy p1rdy p0rdy 0000 adbase 0308 adbase<15:1> 0000 adcpc0 030a irqen1 pend1 swtrg1 trgsrc14 trgsrc13 t rgsrc12 trgsrc11 trgsrc10 irqen0 pend0 swtrg0 trgsrc04 trgsrc03 trgs rc02 trgsrc01 trgsrc00 0000 adcpc1 030c irqen3 pend3 swtrg3 trgsrc34 trgsrc33 t rgsrc32 trgsrc31 trgsrc30 irqen2 pend2 swtrg2 trgsrc24 trgsrc23 trgs rc22 trgsrc21 trgsrc20 0000 adcpc3 0310 irqen6 pend6 swtrg6 trgsrc64 trgs rc63 trgsrc62 trgsrc61 trgsrc60 0000 adcbuf0 0320 adc data buffer 0 xxxx adcbuf1 0322 adc data buffer 1 xxxx adcbuf2 0324 adc data buffer 2 xxxx adcbuf3 0326 adc data buffer 3 xxxx adcbuf4 0328 adc data buffer 4 xxxx adcbuf5 032a adc data buffer 5 xxxx adcbuf6 032c adc data buffer 6 xxxx adcbuf7 032e adc data buffer 7 xxxx adcbuf12 0338 adc data buffer 12 xxxx adcbuf13 033a adc data buffer 13 xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 66 ? 2008-2014 microchip technology inc. table 4-30: high-speed 10-bit adc register map for dspic33fj16gs504 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adcon 0300 adon adsidlslowclk g s w t r g form eie order seqsamp asyncsamp adcs2 adcs1 adcs0 0003 adpcfg 0302 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 adstat 0306 p6rdy p5rdy p4rdy p3rdy p2rdy p1rdy p0rdy 0000 adbase 0308 adbase<15:1> 0000 adcpc0 030a irqen1 pend1 swtrg1 trgsrc14 trgsrc13 trgsrc12 trgsrc11 t rgsrc10 irqen0 pend0 swtrg0 trgsrc04 t rgsrc03 trgsrc02 t rgsrc01 trgsrc00 0000 adcpc1 030c irqen3 pend3 swtrg3 trgsrc3 4 trgsrc33 trgsrc32 trgsrc3 1 trgsrc30 irqen2 pend2 swtrg2 trgsrc24 t rgsrc23 trgsrc22 t rgsrc21 trgsrc20 0000 adcpc2 030e irqen5 pend5 swtrg5 trgsrc54 trgsrc53 trgsrc52 trgsrc51 t rgsrc50 irqen4 pend4 swtrg4 trgsrc44 t rgsrc43 trgsrc42 t rgsrc41 trgsrc40 0000 adcpc3 0310 irqen6 pend6 swtrg6 trgsrc64 trgs rc63 trgsrc62 trg src61 trgsrc60 0000 adcbuf0 0320 adc data buffer 0 xxxx adcbuf1 0322 adc data buffer 1 xxxx adcbuf2 0324 adc data buffer 2 xxxx adcbuf3 0326 adc data buffer 3 xxxx adcbuf4 0328 adc data buffer 4 xxxx adcbuf5 032a adc data buffer 5 xxxx adcbuf6 032c adc data buffer 6 xxxx adcbuf7 032e adc data buffer 7 xxxx adcbuf8 0330 adc data buffer 8 xxxx adcbuf9 0332 adc data buffer 9 xxxx adcbuf10 0334 adc data buffer 10 xxxx adcbuf11 0336 adc data buffer 11 xxxx adcbuf12 0338 adc data buffer 12 xxxx adcbuf13 033a adc data buffer 13 xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 67 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-31: analog comparator control regist er map for dspic33fj06gs202 devices only table 4-32: analog comparator control regist er map dspic33fj16gs502/504 devices only file name adr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmpcon1 0540 cmpon cmpsidl dacoe insel1 insel0 extref cmpstat cmppol range 0000 cmpdac1 0542 c m r e f < 9 : 0 > 0000 cmpcon2 0544 cmpon cmpsidl dacoe insel1 insel0 extref cmpstat cmppol range 0000 cmpdac2 0546 c m r e f < 9 : 0 > 0000 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmpcon1 0540 cmpon cmpsidl dacoe insel1 insel0 extref cmpstat cmppol range 0000 cmpdac1 0542 c m r e f < 9 : 0 > 0000 cmpcon2 0544 cmpon cmpsidl dacoe insel1 insel0 extref cmpstat cmppol range 0000 cmpdac2 0546 c m r e f < 9 : 0 > 0000 cmpcon3 0548 cmpon cmpsidl dacoe insel1 insel0 extref cmpstat cmppol range 0000 cmpdac3 054a c m r e f < 9 : 0 > 0000 cmpcon4 054c cmpon cmpsidl dacoe insel1 insel0 extref cmpstat cmppol range 0000 cmpdac4 054e c m r e f < 9 : 0 > 0000 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 68 ? 2008-2014 microchip technology inc. table 4-33: peripheral pin select input register map table 4-34: peripheral pin select outp ut register map for dspic33fj06gs101 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 int1r5 int1r4 int1r3 int1r2 int1r1 int1r0 3f00 rpinr1 0682 int2r5 int2r4 int2r3 int2r2 int2r1 int2r0 003f rpinr2 0684 t1ckr5 t1ckr4 t1ckr3 t1ckr2 t1ckr1 t1ckr0 0000 rpinr3 0686 t3ckr5 t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 t2ckr5 t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 3f3f rpinr7 068e ic2r5 ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 ic1r5 ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 3f3f rpinr11 0696 ocfar5 ocfar4 ocfar3 ocfar2 ocfar1 ocfar0 3f3f rpinr18 06a4 u1ctsr5 u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 u1rxr5 u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 003f rpinr20 06a8 sck1r5 sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 sdi1r5 sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 3f3f rpinr21 06aa ss1r5 ss1r54 ss1r3 ss1r2 ss1r1 ss1r0 0000 rpinr29 06ba flt1r5 flt1r4 flt1r3 flt1r2 flt1r1 flt1r0 3f00 rpinr30 06bc flt3r5 flt3r4 flt3r3 flt3r2 flt3r1 flt3r0 flt2r5 flt2r4 flt2r3 flt2r2 flt2r1 flt2r0 3f3f rpinr31 06be flt5r5 flt5r4 flt5r3 flt5r2 flt5r1 flt5r0 flt4r5 flt4r4 flt4r3 flt4r2 flt4r1 flt4r0 3f3f rpinr32 06c0 flt7r5 flt7r4 flt7r3 flt7r2 flt7r1 flt7r0 flt6r5 flt6r4 flt6r3 flt6r2 flt6r1 flt6r0 3f3f rpinr33 06c2 synci1r5 synci1r4 synci1r3 synci1r2 synci1r1 synci1r0 flt8r5 flt8r4 flt8r3 flt8r2 flt8r1 flt8r0 3f3f rpinr34 06c4 synci2r5 synci2r4 synci2r3 s ynci2r2 synci2r1 synci2r0 3f3f legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06d0 rp1r5 rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 rp0r5 rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 0000 rpor1 06d2 rp3r5 rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 rp2r5 rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 0000 rpor2 06d4 rp5r5 rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 rp4r5 rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 0000 rpor3 06d6 rp7r5 rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 rp6r5 rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 0000 rpor16 06f0 rp33r5 rp33r4 rp33r3 rp33r2 rp33r1 rp33r0 rp32r5 rp32r4 rp32r3 rp32r2 rp32r1 rp32r0 0000 rpor17 06f2 rp35r5 rp35r4 rp35r3 rp35r2 rp35r1 rp35r0 rp34r5 rp34r4 rp34r3 rp34r2 rp34r1 rp34r0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 69 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-35: peripheral pin select output register map for dspic33fj06gs102, dspic33f j06gs202, dspic33fj16gs402 and dspic33fj16gs502 table 4-36: peripheral pin select output register map for dspic33fj16gs404 and dspic33fj16gs504 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06d0 rp1r5 rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 rp0r5 rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 0000 rpor1 06d2 rp3r5 rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 rp2r5 rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 0000 rpor2 06d4 rp5r5 rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 rp4r5 rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 0000 rpor3 06d6 rp7r5 rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 rp6r5 rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 0000 rpor4 06d8 rp9r5 rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 rp8r5 rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 0000 rpor5 06da rp11r5 rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 rp10r5 rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 0000 rpor6 06dc rp13r5 rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 rp12r5 rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 0000 rpor7 06de rp15r5 rp15r4 rp15r3 rp15r2 rp15r1 rp15r0 rp14r5 rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 0000 rpor16 06f0 rp33r5 rp33r4 rp33r3 rp33r2 rp33r1 rp33r0 rp32r5 rp32r4 rp32r3 rp32r2 rp32r1 rp32r0 0000 rpor17 06f2 rp35r5 rp35r4 rp35r3 rp35r2 rp35r1 rp35r0 rp34r5 rp34r4 rp34r3 rp34r2 rp34r1 rp34r0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06d0 rp1r5 rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 rp0r5 rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 0000 rpor1 06d2 rp3r5 rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 rp2r5 rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 0000 rpor2 06d4 rp5r5 rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 rp4r5 rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 0000 rpor3 06d6 rp7r5 rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 rp6r5 rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 0000 rpor4 06d8 rp9r5 rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 rp8r5 rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 0000 rpor5 06da rp11r5 rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 rp10r5 rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 0000 rpor6 06dc rp13r5 rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 rp12r5 rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 0000 rpor7 06de rp15r5 rp15r4 rp15r3 rp15r2 rp15r1 rp15r0 rp14r5 rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 0000 rpor8 06e0 rp17r5 rp17r4 rp17r3 rp17r2 rp17r1 rp17r0 rp16r5 rp16r4 rp16r3 rp16r2 rp16r1 rp16r0 0000 rpor9 06e2 rp19r5 rp19r4 rp19r3 rp19r2 rp19r1 rp19r0 rp18r5 rp18r4 rp18r3 rp18r2 rp18r1 rp18r0 0000 rpor10 06e4 rp21r5 rp21r4 rp21r3 rp21r2 rp21r1 rp21r0 rp20r5 rp20r4 rp20r3 rp20r2 rp20r1 rp20r0 0000 rpor11 06e6 rp23r5 rp23r4 rp23r3 rp23r2 rp23r1 rp23r0 rp22r5 rp22r4 rp22r3 rp22r2 rp22r1 rp22r0 0000 rpor12 06e8 rp25r5 rp25r4 rp25r3 rp25r2 rp25r1 rp25r0 rp24r5 rp24r4 rp24r3 rp24r2 rp24r1 rp24r0 0000 rpor13 06ea rp27r5 rp27r4 rp27r3 rp27r2 rp27r1 rp27r0 rp26r5 rp26r4 rp26r3 rp26r2 rp26r1 rp26r0 0000 rpor14 06ec rp29r5 rp29r4 rp29r3 rp29r2 rp29r1 rp29r0 rp28r5 rp28r4 rp28r3 rp28r2 rp28r1 rp28r0 0000 rpor16 06f0 rp33r5 rp33r4 rp33r3 rp33r2 rp33r1 rp33r0 rp32r5 rp32r4 rp32r3 rp32r2 rp32r1 rp32r0 0000 rpor17 06f2 rp35r5 rp35r4 rp35r3 rp35r2 rp35r1 rp35r0 rp34r5 rp34r4 rp34r3 rp34r2 rp34r1 rp34r0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 70 ? 2008-2014 microchip technology inc. table 4-37: porta register map table 4-38: portb register map for dspic33fj06gs101 table 4-39: portb register map for dspic33fj06gs102, dspic33fj06gs202, dspic33fj 16gs402, dspic33fj16gs404, dspic33fj16gs502 and dspic33fj16gs504 table 4-40: portc register map for dspic33fj16gs404 and dspic33fj16gs504 file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 trisa<4:0> 001f porta 02c2 r a < 4 : 0 > xxxx lata 02c4 l a t a < 4 : 0 > 0000 odca 02c6 odca<4:3> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<7:0> 00ff portb 02ca r b < 7 : 0 > xxxx latb 02cc latb<7:0> 0000 odcb 02ce o d c b < 7 : 6 > odcb4 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:0> ffff portb 02ca rb<15:0> xxxx latb 02cc latb<15:0> 0000 odcb 02ce odcb<15:11> odcb<8:6> odcb4 ( 1 ) 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this bit is not available on dspic33fj06gs202/502 devices. sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 02d0 trisc<13:0> 3fff portc 02d2 rc<13:0> xxxx latc 02d4 latc<13:0> 0000 odcc 02d6 odcc<13:11> odcc<8:3> odcc0 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 71 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 4-41: system control register map table 4-42: nvm register map table 4-43: pmd register map for dspic33fj06gs101 devices only table 4-44: pmd register map for dspic33fj06gs102 devices only file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr cm vregs extr swr swdten wdto sleep idle bor por xxxx ( 1 ) osccon 0742 cosc2 cosc1 cosc0 nosc2 nosc1 nosc0 clklock iolock lock c f o s w e n 0300 ( 2 ) clkdiv 0744 roi doze2 doze1 doze0 dozen frcdiv2 frcdiv1 frcdiv0 pllpost1 pllpos t0 pllpre4 pllpre3 pllpre2 pllpre1 pllpre0 3040 pllfbd 0746 plldiv<8:0> 0030 refocon 074e roon rosslp rosel rodiv3 rodiv2 rodiv1 rodiv0 0000 osctun 0748 tun<5:0> 0000 aclkcon 0750 enapll apllck selaclk apstsclr2 apstsclr1 apstsclr0 asrcsel frcsel 2300 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: the rcon register reset values are dependent on the type of reset. 2: the osccon register reset values are dependent on the foscx configuration bits and on type of re set. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr e r a s e nvmop3 nvmop2 nvmop1 nvmop0 0000 ( 1 ) nvmkey 0766 nvmkey<7:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: reset value shown is for por only. the value on other reset states is dependent on the state of memor y write or erase operation s at the time of reset. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t2md t1md p w m m d i 2 c 1 m d u1md spi1md adcmd 0000 pmd2 0772 i c 2 m di c 1 m d oc2mdoc1md 0000 pmd3 0774 c m p m d 0000 pmd4 0776 r e f o m d 0000 pmd6 077a p w m 4 m d p w m 1 m d 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t2md t1md p w m m d i 2 c 1 m d u1md spi1md adcmd 0000 pmd2 0772 i c 2 m di c 1 m d oc2mdoc1md 0000 pmd3 0774 c m p m d 0000 pmd4 0776 r e f o m d 0000 pmd6 077a pwm2md pwm1md 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 72 ? 2008-2014 microchip technology inc. table 4-45: pmd register map for dspic33fj06gs202 devices only table 4-46: pmd register map for dspic33fj16gs402 and dspic33fj16gs404 devices only table 4-47: pmd register map for dspic33fj16gs502 and dspic33fj16gs504 devices only sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t2md t1md p w m m d i 2 c 1 m d u1md spi1md adcmd 0000 pmd2 0772 i c 1 m d oc1md 0000 pmd3 0774 c m p m d 0000 pmd4 0776 r e f o m d 0000 pmd6 077a pwm2md pwm1md 0000 pmd7 077c cmp2md cmp1md 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t3md t2md t1md p w m m d i 2 c 1 m d u1md spi1md adcmd 0000 pmd2 0772 i c 2 m di c 1 m d oc2mdoc1md 0000 pmd3 0774 0000 pmd4 0776 r e f o m d 0000 pmd6 077a pwm3md pwm2md pwm1md 0000 pmd7 077c 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t3md t2md t1md p w m m d i 2 c 1 m d u1md spi1md adcmd 0000 pmd2 0772 i c 2 m di c 1 m d oc2mdoc1md 0000 pmd3 0774 c m p m d 0000 pmd4 0776 r e f o m d 0000 pmd6 077a pwm4md pwm3md pwm2md pwm1md 0000 pmd7 077c cmp4md cmp3md cmp2md cmp1md 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 73 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 4.2.6 software stack in addition to its use as a working register, the w15 register in the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices is also used as a software stack pointer. the stack pointer always points to the first available free word and grows from lower to higher addresses. it predecrements for stack pops and post-increments for stack pushes, as shown in figure 4-6 . for a pc push during any call instruc- tion, the msb of the pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit register (splim) associated with the stack pointer sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to 0 because all stack operations must be word-aligned. whenever an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim register are equal and a push operation is performed, a stack error trap will not occur. the stack error trap will occur on a subsequent push operation. for example, to cause a stack error trap when the stack grows beyond address 0x1000 in ram, initialize the splim with the value 0x0ffe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0x0800. this prevents the stack from interfering with the special function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 4-6: call stack frame 4.3 instruction addressing modes the addressing modes shown in ta b l e 4 - 4 8 form the basis of the addressing modes optimized to support the specific features of individual instructions. the addressing modes provided in the mac class of instructions differ from those in the other instruction types. 4.3.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 4.3.2 mcu instructions the three-operand mcu instructions are of the form: operand 3 = operand 1 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 74 ? 2008-2014 microchip technology inc. table 4-48: fundamental addressing modes supported 4.3.3 move and accumulator instructions move instructions and the dsp accumulator class of instructions to provide a greater addressing flexibility than other instructions. in addition to the addressing modes supported by most mcu instructions, move and accumulator instructions also support register indirect with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: register direct register indirect register indirect post-modified register indirect pre-modified register indirect with register offset (indexed) register indirect with literal offset 8-bit literal 16-bit literal 4.3.4 mac instructions the dual source operand dsp instructions ( clr , ed , edac , mac , mpy , mpy.n , movsac and msc ), also referred to as mac instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. the two-source operand prefetch registers must be members of the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu, and w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must, therefore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: register indirect register indirect post-modified by 2 register indirect post-modified by 4 register indirect post-modified by 6 register indirect with register offset (indexed) 4.3.5 other instructions besides the addressing modes outlined previously, some instructions use literal constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the effective address (ea). register indirect post-modified the contents of wn forms the ea. wn is post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incremented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. how- ever, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing mode is available only for w9 (in x space) and w11 (in y space). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 75 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 4.4 modulo addressing modulo addressing mode is a method used to provide an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. modulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for modulo addressing since these two registers are used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incre- menting buffers), or end address (for decrementing buffers), based upon the direction of the buffer. the only exception to the usage restrictions is for buffers that have a power-of-two length. as these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). 4.4.1 start and end address the modulo addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see table 4-1 ). the length of a circular buffer is not directly specified. it is determined by the difference between the corresponding start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.4.2 w address register selection the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags as well as a w register field to specify the w address registers. the xwm and ywm fields select the registers that will operate with modulo addressing: if xwm = 15 , x ragu and x wagu modulo addressing is disabled. if ywm = 15 , y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see ta b l e 4 - 1 ). modulo addressing is enabled for x data space when xwm is set to any value other than 15 and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm) to which modulo addressing is to be applied is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than 15 and the ymoden bit is set at modcon<14>. figure 4-7: modulo address ing operation example note: y space modulo addressing ea calcula- tions assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100, w0 mov w0, xmodsrt ;set modulo start address mov #0x1163, w0 mov w0, modend ;set modulo end address mov #0x8001, w0 mov w0, modcon ;enable w1, x agu for modulo mov #0x0000, w0 ;w0 holds buffer fill value mov #0x1110, w1 ;point w1 to buffer do again, #0x31 ;fill the 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0, w0 ;increment the fill value downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 76 ? 2008-2014 microchip technology inc. 4.4.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. address boundaries check for addresses equal to: the upper boundary addresses for incrementing buffers the lower boundary addresses for decrementing buffers the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). address changes can, therefore, jump beyond boundaries and still be adjusted correctly. 4.5 bit-reversed addressing bit-reversed addressing mode is intended to simplify data re-ordering for radix-2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.5.1 bit-reversed addressing implementation bit-reversed addressing mode is enabled in any of these situations: bwm bits (w register selection) in the modcon register are any value other than 15 (the stack cannot be accessed using bit-reversed addressing) the bren bit is set in the xbrev register the addressing mode used is register indirect with pre-increment or post-increment if the length of a bit-reversed buffer is m = 2 n bytes, the last n bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier, or pivot point, which is typically a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is executed only for register indirect with pre-increment or post- increment addressing and word-sized data writes. it will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. when bit-reversed addressing is active, the w address pointer is always added to the address modifier (xb), and the offset associated with the regis- ter indirect addressing mode is ignored. in addition, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren (xbrev<15>) bit, a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre- modify or post-modify addressing mode is used to compute the effective address. when an address offset (such as [w7 + w2]) is used, modulo addressing correction is performed but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. if an application attempts to do so, bit-reversed addressing will assume priority when active for the x wagu and x wagu; modulo addressing will be dis- abled. however, modulo addressing will continue to function in the x ragu. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 77 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 4-8: bit-reversed address example table 4-49: bit-reversed address sequence (16-entry) normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 78 ? 2008-2014 microchip technology inc. 4.6 interfacing program and data memory spaces the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the dspic33fj06gs101/ x02 and dspic33fj16gsx02/x04 architecture provides two methods by which program space can be accessed during operation: using table instructions to access individual bytes or words anywhere in the program space remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. the application can only access the least significant word of the program word. 4.6.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table page register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the most significant bit of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility register (psvpag) is used to define a 16k word page in the program space. when the most significant bit of the ea is 1 , psvpag is concatenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike table operations, this limits remapping operations strictly to the user memory area. table 4-50 and figure 4-9 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> refers to a program space word, and d<15:0> refers to a data space word. table 4-50: program space address construction access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> data ea<14:0> ( 1 ) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always 1 in this case, but is not used in calculating the program space address. bit 15 of the address is psvpag<0>. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 79 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 4-9: data access from program space address generation 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the least significant bit (lsb) of program space addresses is always fixed as 0 to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word-aligned. table read operations are permitted in the configuration memory space. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 80 ? 2008-2014 microchip technology inc. 4.6.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. tblrdl (table read low): - in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). - in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is 1 ; the lower byte is selected when it is 0 . tblrdh ( table read high): - in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the phantom byte, will always be 0 . - in byte mode, this instruction maps the upper or lower byte of the program word to d<7:0> of the data address, in the tblrdl instruction. the data is always 0 when the upper phantom byte is selected (byte select = 1 ). similarly, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 flash program memory . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user and con- figuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-10: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 phantom byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x000000 0x800000 0x020000 0x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 81 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 4.6.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this option provides transparent access to stored constant data from the data space without the need to use special instructions (such as tblrdl/h ). program space access through the data space occurs if the most significant bit of the data space ea is 1 and program space visibility (psv) is enabled by setting the psv bit in the core control register (corcon<2>). the location of the program memory space to be mapped into the data space is determined by the program space visibility page register (psvpag). this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag functions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. although each data space address 8000h and higher maps directly into a corresponding program memory address (see figure 4-11 ), only the lower 16 bits of the 24-bit program word are used to contain the data. the upper 8 bits of any program space location used as data should be programmed with 1111 1111 or 0000 0000 to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions require one instruction cycle in addition to the specified execution time. all other instructions require two instruction cycles in addition to the specified execution time. for operations that use psv, and are executed inside a repeat loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: execution in the first iteration execution in the last iteration execution prior to exiting the loop due to an interrupt execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction using psv to access data, to execute in a single cycle. figure 4-11: program space visibility operation note: psv access is temporarily disabled during table reads/writes. 23 15 0 psvpag data space program space 0x00000x8000 0xffff 02 0x000000 0x800000 0x010000 0x018000 when corcon<2> = 1 and ea<15> = 1 : the data in the page designated by psvpag is mapped into the upper half of the data memory space... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address. psv area downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 82 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 83 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 5.0 flash program memory the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices contain internal flash program memory for storing and executing application code. the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in two ways: in-circuit serial programming? (icsp?) programming capability run-time self-programming (rtsp) icsp allows a dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 device to be serially programmed while in the end application circuit. this is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: pgecx/pgedx, and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data, either in blocks or rows of 64 instructions (192 bytes) at a time, or a single program memory word, and erase program memory in blocks or pages of 512 instructions (1536 bytes) at a time. 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits<7:0> of the tblpag register and the effective address (ea) from a w register specified in the table instruction, as shown in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to flash programming (ds70191) in the dspic33f/pic24h family reference manual? , which is avail- able from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 84 ? 2008-2014 microchip technology inc. 5.2 rtsp operation the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. table 24-12 shows typical erase and programming times. the 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. the program memory implements holding buffers that can contain 64 instructions of programming data. prior to the actual programming operation, the write data must be loaded into the buffers sequentially. the instruction words loaded must always be from a group of 64 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. a total of 64 tblwtl and tblwth instructions are required to load the instructions. all of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. a programming cycle is required for programming each row. 5.3 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. the processor stalls (waits) until the programming operation is finished. the programming time depends on the frc accuracy (see table 24-20 ) and the value of the frc oscillator tuning register (see register 8-4 ). use the following formula to calculate the minimum and maximum values for the row write time, page erase time, and word write cycle time parameters (see table 24-12 ). equation 5-1: programming time for example, if the device is operating at +125c, the frc accuracy will be 5%. if the tun<5:0> bits (see register 8-4 ) are set to b111111 , the minimum row write time is equal to equation 5-2 . equation 5-2: minimum row write time the maximum row write time is equal to equation 5-3 . equation 5-3: maximum row write time setting the wr bit (nvmcon<15>) starts the opera- tion, and the wr bit is automatically cleared when the operation is finished. 5.4 control registers two sfrs are used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register ( register 5-1 ) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. nvmkey is a write-only register that is used for write protection. to start a pr ogramming or erase sequence, the user application must consecutively write 0x55 and 0xaa to the nvmkey register. refer to section 5.3 programming operations for further details. t 7.37 mhz frc accuracy ?? % frc tuning ?? % ? ? ------------------------------------------------------------------------------------------------------------ ------------- - t rw 11064 cycles 7.37 mhz 10.05 + ?? 1 0.00375 ? ?? ? ? ---------------------------------------------------------------------------------------------- 1.435 ms = = t rw 11064 cycles 7.37 mhz 10.05 ? ?? 1 0.00375 ? ?? ? ? --------------------------------------------------------------------------------------------- - 1.586 ms = = downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 85 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 5-1: nvmcon: flash memory control register r/so-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) u-0 u-0 u-0 u-0 u-0 wr wren wrerr bit 15 bit 8 u-0 r/w-0 ( 1 ) u-0 u-0 r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) erase n v m o p 3 ( 2 ) nvmop2 ( 2 ) nvmop1 ( 2 ) nvmop0 ( 2 ) bit 7 bit 0 legend: so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 wr: write control bit ( 1 ) 1 = initiates a flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit ( 1 ) 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit ( 1 ) 1 = an improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as 0 bit 6 erase: erase/program enable bit ( 1 ) 1 = performs the erase operation specified by nvmop<3:0> on the next wr command 0 = performs the program operation specified by nvmop<3:0> on the next wr command bit 5-4 unimplemented: read as 0 bit 3-0 nvmop<3:0>: nvm operation select bits ( 1 , 2 ) if erase = 1 : 1111 = memory bulk erase operation 1101 = erase general segment 0011 = no operation 0010 = memory page erase operation 0001 = no operation 0000 = erase a single configuration register byte if erase = 0 : 1111 = no operation 1101 = no operation 0011 = memory word program operation 0010 = no operation 0001 = memory row program operation 0000 = program a single configuration register byte note 1: these bits can only be reset on por. 2: all other combinations of nvmop<3:0> are unimplemented. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 86 ? 2008-2014 microchip technology inc. register 5-2: nvmkey: nonvolatile memory key register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 nvmkey<7:0>: nonvolatile memory key bits (write-only) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 87 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 5.4.1 programming algorithm for flash program memory one row of program flash memory can be programmed at a time. to achieve this, it is necessary to erase the 8-row erase page that contains the desired row. the general process is: 1. read eight rows of program memory (512 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the block (see example 5-1 ): a) set the nvmop<3:0> bits (nvmcon<3:0>) to 0010 to configure for block erase. set the erase (nvmcon<6>) and wren (nvmcon<14>) bits. b) write the starting address of the page to be erased into the tblpag and w registers. c) write 0x55 to nvmkey. d) write 0xaa to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the duration of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 64 instructions from data ram into the program memory buffers (see example 5-2 ). 5. write the program block to flash memory: a) set the nvmop<3:0> bits to 0001 to configure for row programming. clear the erase bit and set the wren bit. b) write 0x55 to the nvmkey register. c) write 0xaa to the nvmkey register. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash memory is done, the wr bit is cleared automatically. 6. repeat steps 4 and 5, using the next available 64 instructions from the block in data ram by incre- menting the value in the tblpag register, until all 512 instructions are written back to flash memory. for protection against accidental operations, the write initiate sequence for the nvmkey register must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user application must wait for the pro- gramming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 5-3 . example 5-1: erasing a program memory page ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea[15:0] pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 88 ? 2008-2014 microchip technology inc. example 5-2: loading the write buffers example 5-3: initiating a programming sequence ; set up nvmcon for row programming operations mov #0x4001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 63rd_program_word mov #low_word_31, w2 ; mov #high_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the nop ; erase command is asserted downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 89 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: por: power-on reset bor: brown-out reset mclr : master clear pin reset swr: software reset instruction wdto: watchdog timer reset cm: configuration mismatch reset trapr: trap conflict reset iopuwr: illegal condition device reset - illegal opcode reset - uninitialized w register reset - security reset a simplified block diagram of the reset module is shown in figure 6-1 . any active source of reset will make the sysrst signal active. on system reset, some of the registers associated with the cpu and peripherals are forced to a known reset state and some are unaffected. all types of device reset set a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1 ). a por clears all the bits, except for the por bit (rcon<0>), which is set. the user application can set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. figure 6-1: reset sy stem block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to reset (ds70192) in the dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: refer to the specific peripheral section or section 3.0 cpu of this data sheet for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset is meaningful. mclr v dd internal regulator bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 90 ? 2008-2014 microchip technology inc. register 6-1: rcon: re set control register ( 1 ) r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 trapr iopuwr c mv r e g s bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten ( 2 ) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w register reset has not occurred bit 13-10 unimplemented: read as 0 bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred 0 = a configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into standby mode during sleep bit 7 extr: external reset pin (mclr ) bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset flag (instruction) bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit ( 2 ) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in soft ware does not cause a device reset. 2: if the fwdten configuration bit is 1 (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 91 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register ( 1 ) (continued) note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in soft ware does not cause a device reset. 2: if the fwdten configuration bit is 1 (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 92 ? 2008-2014 microchip technology inc. 6.1 system reset the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 families of devices have two types of reset: cold reset warm reset a cold reset is the result of a power-on reset (por) or a brown-out reset (bor). on a cold reset, the fnoscx configuration bits in the fosc configuration register select the device clock source. a warm reset is the result of all the other reset sources, including the reset instruction. on warm reset, the device will continue to operate from the current clock source as indicated by the current oscillator selection (cosc<2:0>) bits in the oscillator control (osccon<14:12>) register. the device is kept in a reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. the sequence in which this occurs is detailed in figure 6-2 . table 6-1: oscillator delay oscillator mode oscillator startup delay oscillator startup timer pll lock time total delay frc, frcdiv16, frcdivn t oscd ( 1 ) t oscd ( 1 ) frcpll t oscd ( 1 ) t lock ( 3 ) t oscd + t lock ( 1 , 3 ) xt t oscd ( 1 ) t ost ( 2 ) t oscd + t ost ( 1 , 2 ) hs t oscd ( 1 ) t ost ( 2 ) t oscd + t ost ( 1 , 2 ) e c xtpll t oscd ( 1 ) t ost ( 2 ) t lock ( 3 ) t oscd + t ost + t lock ( 1 , 2 , 3 ) hspll t oscd ( 1 ) t ost ( 2 ) t lock ( 3 ) t oscd + t ost + t lock ( 1 , 2 , 3 ) ecpll t lock ( 3 ) t lock ( 3 ) lprc t oscd ( 1 ) t oscd ( 1 ) note 1: t oscd = oscillator start-up delay (1.1 ? s max for frc, 70 ? s max for lprc). crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: t ost = oscillator start-up timer delay (1024 oscillator clock period). for example, t ost = 102.4 ? s for a 10 mhz crystal and t ost = 32 ms for a 32 khz crystal. 3: t lock = pll lock time (1.5 ms nominal) if pll is enabled. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 93 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 6-2: system reset timing reset run device status v dd v por v bor por reset bor reset sysrst t pwrt t por t bor oscillator clock t oscd t ost t lock time fscm t fscm 1 2 3 4 5 6 note 1: por reset: a por circuit holds the device in reset when the power supply is turned on. the por circuit is active until v dd crosses the v por threshold and the delay, t por , has elapsed. 2: bor reset: the on-chip voltage regulator has a bor circuit that keeps the device in reset until v dd crosses the v bor threshold and the delay, t bor , has elapsed. the delay, t bor , ensures the voltage regulator output becomes stable. 3: pwrt timer: the programmable power-up timer continues to hold the processor in reset for a specific period of time (t pwrt ) after a bor. the delay, t pwrt , ensures that the system power supplies have stabilized at the appro- priate level for full-speed operation. after the delay, t pwrt has elapsed and the sysrst becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. 4: oscillator delay: the total delay for the clock to be ready for various clock source selections is given in table 6-1 . refer to section 8.0 oscillator configuration for more information. 5: when the oscillator clock is ready, the processor begins execution from location, 0x000000. the user application programs a goto instruction at the reset address, which redire cts program execution to the appropriate start-up routine. 6: if the fail-safe clock monitor (fscm) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, t fscm , has elapsed. table 6-2: oscillator delay symbol parameter value v por por threshold 1.8v nominal t por por extension time 30 ? s maximum v bor bor threshold 2.5v nominal t bor bor extension time 100 ? s maximum t pwrt programmable power-up time delay 0-128 ms nominal t fscm fail-safe clock monitor delay 900 ? s maximum note: when the device exits the reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device may not function correctly. the user application must ensure that the delay between the time power is first applied, and the time sysrst becomes inactive, is long enough to get all operating parameters within specification. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 94 ? 2008-2014 microchip technology inc. 6.2 power-on reset (por) a power-on reset (por) circuit ensures the device is reset from power-on. the por circuit is active until v dd crosses the v por threshold and the delay, t por , has elapsed. the delay, t por , ensures the internal device bias circuits become stable. the device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the por. refer to section 24.0 electrical characteristics for details. the por status (por) bit in the reset control (rcon<0>) register is set to indicate the power-on reset. 6.2.1 brown-out reset (bor) and power-up timer (pwrt) the on-chip regulator has a brown-out reset (bor) circuit that resets the device when the v dd is too low (v dd < v bor ) for proper device operation. the bor circuit keeps the device in reset until v dd crosses the v bor threshold and the delay, t bor , has elapsed. the delay, t bor , ensures the voltage regulator output becomes stable. the bor status (bor) bit in the reset control (rcon<1>) register is set to indicate the brown-out reset. the device will not run at full speed after a bor as the v dd should rise to acceptable levels for full-speed operation. the pwrt provides power-up time delay (t pwrt ) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the sysrst is released. the power-up timer delay (t pwrt ) is programmed by the power-on reset timer value select (fpwrt<2:0>) bits in the fpor configuration (fpor<2:0>) register, which provides eight settings (from 0 ms to 128 ms). refer to section 21.0 special features for further details. figure 6-3 shows the typical brown-out scenarios. the reset delay (t bor + t pwrt ) is initiated each time v dd rises above the v bor trip point. figure 6-3: brown-o ut situations v dd sysrst v bor v dd sysrst v bor v dd sysrst v bor t bor + t pwrt v dd dips before pwrt expires t bor + t pwrt t bor + t pwrt downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 95 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 6.3 external reset (extr) the external reset is generated by driving the mclr pin low. the mclr pin is a schmitt trigger input with an additional glitch filter. reset pulses that are longer than the minimum pulse width will generate a reset. refer to section 24.0 electrical characteristics for minimum pulse width specifications. the external reset (mclr ) pin (extr) bit in the reset control (rcon) register is set to indicate the mclr reset. 6.3.0.1 external supervisory circuit many systems have external supervisory circuits that generate reset signals to reset multiple devices in the system. this external reset signal can be directly connected to the mclr pin to reset the device when the rest of the system is reset. 6.3.0.2 internal supervisory circuit when using the internal power supervisory circuit to reset the device, the external reset pin (mclr ) should be tied directly or resistively to v dd . in this case, the mclr pin will not be used to generate a reset. the external reset pin (mclr ) does not have an internal pull-up and must not be left unconnected. 6.4 software reset instruction (swr) whenever the reset instruction is executed, the device will assert sysrst , placing the device in a special reset state. this reset state will not re-initialize the clock. the clock source in effect prior to the reset instruction will remain. sysrst is released at the next instruction cycle and the reset vector fetch will commence. the software reset (swr) flag (instruction) in the reset control (rcon<6>) register is set to indicate the software reset. 6.5 watchdog timer time-out reset (wdto) whenever a watchdog time-out occurs, the device will asynchronously assert sysrst . the clock source will remain unchanged. a wdt time-out during sleep or idle mode will wake-up the processor, but will not reset the processor. the watchdog timer time-out (wdto) flag in the reset control (rcon<4>) register is set to indicate the watchdog timer reset. refer to section 21.4 watchdog timer (wdt) for more information on the watchdog timer reset. 6.6 trap conflict reset if a lower priority hard trap occurs while a higher priority trap is being processed, a hard trap conflict reset occurs. the hard traps include exceptions of priority levels 13 through 15, inclusive. the address error (level 13) and oscillator error (level 14) traps fall into this category. the trap reset (trapr) flag in the reset control (rcon<15>) register is set to indicate the trap conflict reset. refer to section 7.0 interrupt controller for more information on trap conflict resets. 6.7 configuration mismatch reset to maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. if an unexpected change in any of the registers occur (such as cell disturbances caused by esd or other external events), a configuration mismatch reset occurs. the configuration mismatch (cm) flag in the reset control (rcon<9>) register is set to indicate the configuration mismatch reset. refer to section 10.0 i/o ports for more information on the configuration mismatch reset. 6.8 illegal condition device reset an illegal condition device reset occurs due to the following sources: illegal opcode reset uninitialized w register reset security reset the illegal opcode or uninitialized w access reset (iopuwr) flag in the reset control (rcon<14>) register is set to indicate the illegal condition device reset. 6.8.1 illegal opcode reset a device reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. the illegal opcode reset function can prevent the device from executing program memory sections that are used to store constant data. to take advantage of the illegal opcode reset, use only the lower 16 bits of each program memory section to store the data values. the upper 8 bits should be programmed with 3fh, which is an illegal opcode value. note: the configuration mismatch reset feature and associated reset flag are not available on all devices. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 96 ? 2008-2014 microchip technology inc. 6.8.2 uninitialized w register reset any attempt to use the uninitialized w register as an address pointer will reset the device. the w register array (with the exception of w15) is cleared during all resets and is considered uninitialized until written to. 6.8.3 security reset if a program flow change (pfc) or vector flow change (vfc) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a security reset. the pfc occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine or other form of branch instruction. the vfc occurs when the program counter is reloaded with an interrupt or trap vector. refer to section 21.8 code protection and codeguard? security for more information on security reset. 6.9 using the rcon status bits the user application can read the reset control (rcon) register after any device reset to determine the cause of the reset. table 6-3 provides a summary of the reset flag bit operation. table 6-3: reset flag bit operation note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. flag bit set by: cleared by: trapr (rcon<15>) trap conflict event por, bor iopwr (rcon<14>) illegal opcode or uninitialized w register access or security reset por, bor cm (rcon<9>) configuration mismatch por, bor extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por, bor wdto (rcon<4>) wdt time-out pwrsav instruction, clrwdt instruction, por, bor sleep (rcon<3>) pwrsav #sleep instruction por, bor idle (rcon<2>) pwrsav #idle instruction por, bor bor (rcon<1>) por, bor por (rcon<0>) por note: all reset flag bits can be set or cleared by user software. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 97 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 7.0 interrupt controller the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 cpu. it has the following features: up to eight processor exceptions and software traps seven user-selectable priority levels interrupt vector table (ivt) with up to 118 vectors a unique vector for each interrupt or exception source fixed priority within a specified user priority level alternate interrupt vector table (aivt) for debug support fixed interrupt entry and return latencies 7.1 interrupt vector table the interrupt vector table (ivt) is shown in figure 7-1 . the ivt resides in program memory, starting at location 000004h. the ivt contains 126 vectors, consisting of eight nonmaskable trap vectors, plus up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit-wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority. this priority is linked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. the ds pic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices implement up to 35 unique interrupts and 4 non-maskable traps. these are summarized in table 7-1 . 7.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 7-1 . access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. the alternate vectors are organized in the same manner as the default vectors. the aivt supports debugging by providing a means to switch between an application and a support environ- ment without requiring the interrupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 7.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices clear their registers in response to a reset, which forces the pc to zero. the digital signal controller then begins program execution at location, 0x000000. a goto instruction at the reset address can redirect program execution to the appropriate start-up routine. note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to interrupts (part iv) (ds70300) in the dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 98 ? 2008-2014 microchip technology inc. figure 7-1: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 interrupt vector table reset C goto instruction 0x000000 reset C goto address 0x000002 reserved 0x000004 oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000014 interrupt vector 1 ~~ ~ interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 ~~ ~ interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe reserved 0x000100 reserved 0x000102 reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000114 interrupt vector 1 ~~ ~ interrupt vector 52 0x00017c interrupt vector 53 0x00017e interrupt vector 54 0x000180 ~~ ~ interrupt vector 116 interrupt vector 117 0x0001fe start of code 0x000200 decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 7-1 for the list of implemented interrupt vectors. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 99 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 7-1: interrupt vectors vector number interrupt request (iqr) ivt address aivt addr ess interrupt source highest natural order priority 8 0 0x000014 0x000114 int0 C external interrupt 0 9 1 0x000016 0x000116 ic1 C input capture 1 10 2 0x000018 0x000118 oc1 C output compare 1 11 3 0x00001a 0x00011a t1 C timer1 12 4 0x00001c 0x00011c reserved 13 5 0x00001e 0x00011e ic2 C input capture 2 14 6 0x000020 0x000120 oc2 C output compare 2 15 7 0x000022 0x000122 t2 C timer2 16 8 0x000024 0x000124 t3 C timer3 17 9 0x000026 0x000126 spi1e C spi1 fault 18 10 0x000028 0x000128 spi1 C spi1 transfer done 19 11 0x00002a 0x00012a u1rx C uart1 receiver 20 12 0x00002c 0x00012c u1tx C uart1 transmitter 21 13 0x00002e 0x00012e adc C adc group convert done 22-23 14-15 0x000030-0x000032 0x000130-0x000132 reserved 24 16 0x000034 0x000134 si2c1 C i2c1 slave event 25 17 0x000036 0x000136 mi2c1 C i2c1 master event 26 18 0x000038 0x000138 cmp1 C analog comparator 1 interrupt 27 19 0x00003a 0x00013a cn C input change notification interrupt 28 20 0x00003c 0x00013c int1 C external interrupt 1 29-36 21-28 0x00003e-0x00004c 0x00013e-0x00014c reserved 37 29 0x00004e 0x00014e int2 C external interrupt 2 38-64 30-56 0x000050-0x000084 0x000150-0x000184 reserved 65 57 0x000086 0x000186 pwm psem special event match 66-72 58-64 0x000088-0x000094 0x000188-0x000194 reserved 73 65 0x000096 0x000196 u1e C uart1 error interrupt 74-101 66-93 0x000098-0x0000ce 0x000198-0x0001ce reserved 102 94 0x0000d0 0x0001d0 pwm1 C pwm1 interrupt 103 95 0x0000d2 0x0001d2 pwm2 C pwm2 interrupt 104 96 0x0000d4 0x0001d4 pwm3 C pwm3 interrupt 105 97 0x0000d6 0x0001d6 pwm4 C pwm4 interrupt 106-110 98-102 0x0000d8-0x0000e0 0x0001d8-0x0001e0 reserved 111 103 0x0000e2 0x00001e2 cmp2 C analog comparator 2 112 104 0x0000e4 0x0001e4 cmp3 C analog comparator 3 113 105 0x0000e6 0x0001e6 cmp4 C analog comparator 4 114-117 106-109 0x0000e8-0x0000ee 0x0001e8-0x0001ee reserved 118 110 0x0000f0 0x0001f0 adc pair 0 convert done 119 111 0x0000f2 0x0001f2 adc pair 1 convert done 120 112 0x0000f4 0x0001f4 adc pair 2 convert done 121 113 0x0000f6 0x0001f6 adc pair 3 convert done 122 114 0x0000f8 0x0001f8 adc pair 4 convert done 123 115 0x0000fa 0x0001fa adc pair 5 convert done 124 116 0x0000fc 0x0001fc adc pair 6 convert done 125 117 0x0000fe 0x0001fe reserved lowest natural order priority downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 100 ? 2008-2014 microchip technology inc. 7.3 interrupt control and status registers the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices implement 27 registers for the interrupt controller: intcon1 intcon2 ifsx iecx ipcx inttreg 7.3.1 intcon1 and intcon2 global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the interrupt nesting disable (nstdis) bit as well as the control and status flags for the processor trap sources. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate interrupt vector table. 7.3.2 ifsx the ifsx registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 iecx the iecx registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. 7.3.4 ipcx the ipcx registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. 7.3.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt pri- ority level, which are latched into the vector number (vecnum<6:0>) and interrupt level (ilr<3:0>) bit fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence that they are listed in table 7-1 . for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit is found in iec0<0> and the int0ip bits are found in the first position of ipc0 (ipc0<2:0>). 7.3.6 status/control registers although they are not specifically part of the interrupt control hardware, two of the cpu control registers contain bits that control interrupt functionality. the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user can change the current cpu priority level by writing to the ipl bits. the corcon register contains the ipl3 bit, which together with ipl<2:0>, indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 7-1 through register 7-35 in the following pages. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 101 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-1: sr: cpu status register ( 1 ) register 7-2: corcon: core control register ( 1 ) r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r -0 r/w-0 oa ob sa sb oab sab da dc bit 15 bit 8 r/w-0 ( 3 ) r/w-0 ( 3 ) r/w-0 ( 3 ) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 ( 2 ) ipl1 ( 2 ) ipl0 ( 2 ) ra n ov z c bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits ( 2 , 3 ) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 3-1 . 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis (intcon1<15>) = 1 . u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 us edt dl2 dl1 dl0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 ( 2 ) psv rnd if bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown u = unimplemented bit, read as 0 bit 3 ipl3: cpu interrupt priority level status bit 3 ( 2 ) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 3-2 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 102 ? 2008-2014 microchip technology inc. register 7-3: intcon1: in terrupt control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 sftacerr div0err matherr addrerr stkerr oscfail bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14 ovaerr: accumulator a overflow trap flag bit 1 = trap was caused by overflow of accumulator a 0 = trap was not caused by overflow of accumulator a bit 13 ovberr: accumulator b overflow trap flag bit 1 = trap was caused by overflow of accumulator b 0 = trap was not caused by overflow of accumulator b bit 12 covaerr: accumulator a catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator a 0 = trap was not caused by catastrophic overflow of accumulator a bit 11 covberr: accumulator b catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator b 0 = trap was not caused by catastrophic overflow of accumulator b bit 10 ovate: accumulator a overflow trap enable bit 1 = trap overflow of accumulator a 0 = trap is disabled bit 9 ovbte: accumulator b overflow trap enable bit 1 = trap overflow of accumulator b 0 = trap is disabled bit 8 covte: catastrophic overflow trap enable bit 1 = trap on catastrophic overflow of accumulator a or b enabled 0 = trap is disabled bit 7 sftacerr: shift accumulator error status bit 1 = math error trap was caused by an invalid accumulator shift 0 = math error trap was not caused by an invalid accumulator shift bit 6 div0err: arithmetic error status bit 1 = math error trap was caused by a divide-by-zero 0 = math error trap was not caused by a divide-by-zero bit 5 unimplemented: read as 0 bit 4 matherr: arithmetic error status bit 1 = math error trap has occurred 0 = math error trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 103 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as 0 register 7-3: intcon1: interrupt control register 1 (continued) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 104 ? 2008-2014 microchip technology inc. register 7-4: intcon2: in terrupt control register 2 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 altivt disi bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as 0 bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 105 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-5: ifs0: interrupt flag status register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adif u1txif u1rxif spi1if spi1eif t3if bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2if oc2if ic2if t1if oc1if ic1if int0if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 adif: adc group conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spi1eif: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as 0 bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 106 ? 2008-2014 microchip technology inc. bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-5: ifs0: interrupt fla g status register 0 (continued) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 107 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-6: ifs1: interrupt flag status register 1 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 i n t 2 i f bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int1if cnif ac1if mi2c1if si2c1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-5 unimplemented: read as 0 bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 ac1if: analog comparator 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 mi2c1if: i2c1 master events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: i2c1 slave events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 108 ? 2008-2014 microchip technology inc. register 7-7: ifs3: interrupt flag status register 3 register 7-8: ifs4: interrupt flag status register 4 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 psemif bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9 psemif: pwm special event match interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8-0 unimplemented: read as 0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 u 1 e i f bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as 0 bit 1 u1eif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 109 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-9: ifs5: interrupt flag status register 5 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 pwm2if pwm1if bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pwm2if: pwm2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 pwm1if: pwm1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 110 ? 2008-2014 microchip technology inc. register 7-10: ifs6: interrupt flag status register 6 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 adcp1if adcp0if a c 4 i fa c 3 i f bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ac2if pwm4if pwm3if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 adcp1if: adc pair 1 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 adcp0if: adc pair 0 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-10 unimplemented: read as 0 bit 9 ac4if: analog comparator 4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 ac3if: analog comparator 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 ac2if: analog comparator 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6-2 unimplemented: read as 0 bit 1 pwm4if: pwm4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 pwm3if: pwm3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 111 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-11: ifs7: interr upt flag status register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcp6if adcp5if adcp4if adcp3if adcp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4 adcp6if: adc pair 6 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 adcp5if: adc pair 5 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 adcp4if: adc pair 4 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 adcp3if: adc pair 3 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 adcp2if: adc pair 2 conversion done interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 112 ? 2008-2014 microchip technology inc. register 7-12: iec0: interrupt enable control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adie u1txie u1rxie spi1ie spi1eie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 adie: adc1 conversion complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 spi1ie: spi1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 spi1eie: spi1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 unimplemented: read as 0 bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 113 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 int0ie: external interrupt 0 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled register 7-12: iec0: interrupt enable control register 0 (continued) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 114 ? 2008-2014 microchip technology inc. register 7-13: iec1: interrupt enable control register 1 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 i n t 2 i e bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int1ie cnie ac1ie mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 int2ie: external interrupt 2 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12-5 unimplemented: read as 0 bit 4 int1ie: external interrupt 1 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 ac1ie: analog comparator 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 mi2c1ie: i2c1 master events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 si2c1ie: i2c1 slave events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 115 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-14: iec3: interrupt enable control register 3 register 7-15: iec4: interrupt enable control register 4 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 psemie bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9 psemie: pwm special event match interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8-0 unimplemented: read as 0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 u 1 e i e bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as 0 bit 1 u1eie: uart1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 unimplemented: read as 0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 116 ? 2008-2014 microchip technology inc. register 7-16: iec5: interrupt enable control register 5 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 pwm2ie pwm1ie bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pwm2ie: pwm2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 14 pwm1ie: pwm1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 117 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-17: iec6: interrupt enable control register 6 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 adcp1ie adcp0ie a c 4 i ea c 3 i e bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ac2ie p w m 4 i ep w m 3 i e bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 adcp1ie: adc pair 1 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 14 adcp0ie: adc pair 0 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13-10 unimplemented: read as 0 bit 9 ac4ie: analog comparator 4 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8 ac3ie: analog comparator 3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7 ac2ie: analog comparator 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 6-2 unimplemented: read as 0 bit 1 pwm4ie: pwm4 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 pwm3ie: pwm3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 118 ? 2008-2014 microchip technology inc. register 7-18: iec7: interrupt enable control register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcp6ie adcp5ie adcp4ie adcp3ie adcp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4 adcp6ie: adc pair 6 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 3 adcp5ie: adc pair 5 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 adcp4ie: adc pair 4 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 adcp3ie: adc pair 3 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 adcp2ie: adc pair 2 conversion done interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 119 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-19: ipc0: interrupt pr iority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 t1ip2 t1ip1 t1ip0 oc1ip2 oc1ip1 oc1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ic1ip2 ic1ip1 ic1ip0 int0ip2 int0ip1 int0ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 120 ? 2008-2014 microchip technology inc. register 7-20: ipc1: interrupt pr iority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 t2ip2 t2ip1 t2ip0 oc2ip2 oc2ip1 oc2ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ic2ip2 ic2ip1 ic2ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 ic2ip<2:0>: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 121 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-21: ipc2: interrupt pr iority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 spi1eip2 spi1eip1 spi1eip0 t3ip2 t3ip1 t3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 spi1eip<2:0>: spi1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 122 ? 2008-2014 microchip technology inc. register 7-22: ipc3: interrupt pr iority control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 adip2 adip1 adip0 u1txip2 u1txip1 u1txip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6-4 adip<2:0>: adc1 conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 123 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-23: ipc4: interrupt pr iority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 cnip2 cnip1 cnip0 ac1ip2 ac1ip1 ac1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 cnip<2:0>: change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 ac1ip<2:0>: analog comparator 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 mi2c1ip<2:0>: i2c1 master events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 si2c1ip<2:0>: i2c1 slave events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 124 ? 2008-2014 microchip technology inc. register 7-24: ipc5: interrupt pr iority control register 5 register 7-25: ipc7: interrupt pr iority control register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 int1ip2 int1ip1 int1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 int2ip2 int2ip1 int2ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 125 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-26: ipc14: interrupt priority control register 14 register 7-27: ipc16: interrupt priority control register 16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 psemip2 psemip1 psemip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6-4 psemip<2:0>: pwm special event match interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as 0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u1eip2 u1eip1 u1eip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6-4 u1eip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 126 ? 2008-2014 microchip technology inc. register 7-28: ipc23: interrupt priority control register 23 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 pwm2ip<2:0>: pwm2 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 pwm1ip<2:0>: pwm1 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 127 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-29: ipc24: interrupt priority control register 24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 pwm4ip2 pwm4ip1 pwm4ip0 pwm3ip2 pwm3ip1 pwm3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6-4 pwm4ip<2:0>: pwm4 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 pwm3ip<2:0>: pwm3 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 128 ? 2008-2014 microchip technology inc. register 7-30: ipc25: interrupt priority control register 25 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ac2ip2 ac2ip1 ac2ip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 ac2ip<2:0>: analog comparator 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-01 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 129 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-31: ipc26: interrupt priority control register 26 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ac4ip2 ac4ip1 ac4ip0 ac3ip2 ac3ip1 ac3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6-4 ac4ip<2:0>: analog comparator 4 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 ac3ip<2:0>: analog comparator 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 130 ? 2008-2014 microchip technology inc. register 7-32: ipc27: interrupt priority control register 27 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 adcp1ip2 adcp1ip1 adcp1ip0 adcp0ip2 adcp0ip1 adcp0ip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 adcp1ip<2:0>: adc pair 1 conversion done interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 adcp0ip<2:0>: adc pair 0 conversion done interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 131 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-33: ipc28: interrupt priority control register 28 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 adcp5ip2 adcp5ip1 adcp5ip0 adcp4ip2 adcp4ip1 adcp4ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 adcp3ip2 adcp3ip1 adcp3ip0 adcp2ip2 adcp2ip1 adcp2ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 adcp5ip<2:0>: adc pair 5 conversion done interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 adcp4ip<2:0>: adc pair 4 conversion done interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 adcp3ip<2:0>: adc pair 3 conversion done interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 adcp2ip<2:0>: adc pair 2 conversion done interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 132 ? 2008-2014 microchip technology inc. register 7-34: ipc29: interrupt priority control register 29 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 adcp6ip2 adcp6ip1 adcp6ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 adcp6ip<2:0>: adc pair 6 conversion done interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 133 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 7-35: inttreg: interrupt control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ilr3 ilr2 ilr1 ilr0 bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as 0 bit 6-0 vecnum<6:0>: vector number of pending interrupt bits 0111111 = interrupt vector pending is number 135 0000001 = interrupt vector pending is number 9 0000000 = interrupt vector pending is number 8 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 134 ? 2008-2014 microchip technology inc. 7.4 interrupt setup procedures 7.4.1 initialization complete the following steps to configure an interrupt source at initialization: 1. set the nstdis bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate iecx register. 7.4.2 interrupt service routine the method used to declare an isr and initialize the ivt with the correct vector address depends on the programming language (c or assembler) and the language development toolsuite used to develop the application. in general, the user application must clear the interrupt flag in the appropriate ifsx register for the source of interrupt that the isr handles. otherwise, program will re-enter the isr immediately after exiting the routine. if the isr is coded in assembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 7.4.3 trap service routine a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 7.4.4 interrupt disable the following steps outline the procedure to disable all user interrupts: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value 0xe0 with srl. to enable user interrupts, the pop instruction can be used to restore the previous sr value. the disi instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized such that all user interrupt sources are assigned to priority level 4. note: only user interrupts with a priority level of 7 or lower can be disabled. trap sources (level 8-level 15) cannot be disabled. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 135 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 8.0 oscillator configuration the oscillator system provides: external and internal oscillator options as clock sources an on-chip phase-locked loop (pll) to scale the internal operating frequency to the required system clock frequency an internal frc oscillator that can also be used with the pll, thereby allowing full-speed operation without any external clock generation hardware clock switching between various clock sources programmable clock postscaler for system power savings a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures a clock control register (osccon) nonvolatile configuration bits for main oscillator selection auxiliary pll for adc and pwm a simplified diagram of the oscillator system is shown in figure 8-1 . figure 8-1: oscillator system diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to oscillator (part iv) (ds70307) in the ?dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. xtpll, hspll, xt, hs, ec frcdiv<2:0> wdt, pwrt, fscm frcdivn frcdiv16 ecpll, frcpll nosc<2:0> fnosc<2:0> reset frc oscillator lprc oscillator doze<2:0> s3 s1 s2 s1/s3 s7 s6 frc lprc s0s5 16 clock switch s7 clock fail tun<5:0> pll (1) f cy (3) f osc frcdiv doze n aclk selaclk apstsclr<2:0> to pwm/adc (1) enapll poscmd<1:0> f vco (1) apll (1) x16 asrcsel frcsel poscclk frcclk frcclk poscclk n rosel rodiv<3:0> refclko poscclk reference clock generation auxiliary clock generation rpx note 1: see section 8.1.3 pll configuration and section 8.2 auxiliary clock generation for configuration restrictions. 2: if the oscillator is used with xt or hs modes, an external parallel resistor with the value of 1 m ? must be connected. 3: the term, f p , refers to the clock source for all the peripherals, while f cy refers to the clock source for the cpu. throughout this doc- ument, f cy and f p are used interchangeably, except in the case of doze mode. f p and f cy will be different when doze mode is used in any ratio other than 1:1, which is the default. f vco (1) f osc f p (3) osc2 osc1 primary oscillator r (2) 2 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 136 ? 2008-2014 microchip technology inc. 8.1 cpu clocking system the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices provide six system clock options: fast rc (frc) oscillator frc oscillator with pll primary (xt, hs or ec) oscillator primary oscillator with pll low-power rc (lprc) oscillator frc oscillator with postscaler 8.1.1 system clock sources the fast rc (frc) internal oscillator runs at a nominal frequency of 7.37 mhz. user software can tune the frc frequency. user software can optionally specify a factor (ranging from 1:2 to 1:256) by which the frc clock frequency is divided. this factor is selected using the frcdiv<2:0> (clkdiv<10:8>) bits. the primary oscillator can use one of the following as its clock source: xt (crystal): crystals and ceramic resonators in the range of 3 mhz to 10 mhz. the crystal is connected to the osc1 and osc2 pins. hs (high-speed crystal): crystals in the range of 10 mhz to 40 mhz. the crystal is connected to the osc1 and osc2 pins. ec (external clock): the external clock signal is directly applied to the osc1 pin. the lprc internal oscillator runs at a nominal frequency of 32.768 khz. it is also used as a reference clock by the watchdog timer (wdt) and fail-safe clock monitor (fscm). the clock signals generated by the frc and primary oscillators can be optionally applied to an on-chip phase-locked loop (pll) to provide a wide range of output frequencies for device operation. pll configuration is described in section 8.1.3 pll configuration . the frc frequency depends on the frc accuracy (see table 24-20 ) and the value of the frc oscillator tuning register (see register 8-4 ). 8.1.2 system clock selection the oscillator source used at a device power-on reset event is selected using configuration bit settings. the oscillator configuration bit settings are located in the configuration registers in the program memory. (refer to section 21.1 configuration bits for further details.) the initial oscillator selection con- figuration bits, fnosc<2:0> (foscsel<2:0>), and the primary oscillator mode select configuration bits, poscmd<1:0> (fosc<1:0>), select the oscillator source that is used at a power-on reset. the frc primary oscillator is the default (unprogrammed) selection. the configuration bits allow users to choose among 12 different clock modes, shown in tab l e 8 - 1 . the output of the oscillator (or the output of the pll if a pll mode has been selected), f osc , is divided by 2 to generate the device instruction clock (f cy ) and the peripheral clock time base (f p ). f cy defines the operating speed of the device and speeds up to 40 mhz are supported by the dspic33fj06gs101/ x02 and dspic33fj16gsx02/x04 architecture. instruction execution speed or device operating frequency, f cy , is given by equation 8-1 . equation 8-1: device operating frequency table 8-1: configuration bit va lues for clock selection f cy = f osc /2 oscillator mode oscillator source poscmd<1:0> fnosc<2:0> see notes fast rc oscillator with divide-by-n (frcdivn) internal xx 111 1 , 2 fast rc oscillator with divide-by-16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 reserved reserved xx 100 primary oscillator (hs) with pll (hspll) primary 10 011 primary oscillator (xt) with pll (xtpll) primary 01 011 primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 1 fast rc oscillator with pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 137 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 8.1.3 pll configuration the primary oscillator and internal frc oscillator can optionally use an on-chip pll to obtain higher speeds of operation. the pll provides significant flexibility in selecting the device operating speed. a block diagram of the pll is shown in figure 8-2 . the output of the primary oscillator or frc, denoted as f in , is divided down by a prescale factor (n1) of 2, 3, ... or 33 before being provided to the plls voltage controlled oscillator (vco). the input to the vco must be selected in the range of 0.8 mhz to 8 mhz. the prescale factor n1 is selected using the pllpre<4:0> bits (clkdiv<4:0>). the pll feedback divisor, selected using the plldiv<8:0> bits (pllfbd<8:0>), provides a factor, m, by which the input to the vco is multiplied. this factor must be selected such that the resulting vco output frequency is in the range of 100 mhz to 200 mhz. the vco output is further divided by a postscale factor, n2. this factor is selected using the pllpost<1:0> bits (clkdiv<7:6>). n2 can be either 2, 4, or 8, and must be selected such that the pll output frequency (f osc ) is in the range of 12.5 mhz to 80 mhz, which generates device operating speeds of 6.25-40 mips. for a primary oscillator or frc oscillator, output f in , the pll output f osc is given by equation 8-2 . equation 8-2: f osc calculation for example, suppose a 10 mhz crystal is being used with the selected oscillator mode of xt with pll (see equation 8-3 ). if pllpre<4:0> = 0 , then n1 = 2. this yields a vco input of 10/2 = 5 mhz, which is within the acceptable range of 0.8-8 mhz. if plldiv<8:0> = 0x1e, then m = 32. this yields a vco output of 5 x 32 = 160 mhz, which is within the 100-200 mhz ranged needed. if pllpost<1:0> = 0 , then n2 = 2. this provides a fosc of 160/2 = 80 mhz. the resultant device operating speed is 80/2 = 40 mips. equation 8-3: xt with pll mode example figure 8-2: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pll block diagram ( ) m n1*n2 f osc = f in * f cy = f osc 2 == 12 ( 10000000 * 32 2 * 2 ) 40 mips 0.8-8.0 mhz here (1) 100-200 mhz here (1) divide-by- 2, 4, 8 divide-by- 2-513 divide-by- 2-33 source (crystal, external pllpre x vco plldiv pllpost clock or internal rc) 12.5-80 mhz here (1) f osc f vco n1 m n2 note 1: this frequency range must be satisfied at all times. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 138 ? 2008-2014 microchip technology inc. 8.2 auxiliary clock generation the auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a pwm or adc. the primary oscillator and internal frc oscillator sources can be used with an auxiliary pll to obtain the auxiliary clock. the auxiliary pll has a fixed 16x multiplication factor. the auxiliary clock has the following configuration restrictions: for proper pwm operation, auxiliary clock genera- tion must be configured for 120 mhz (see parameter os56 in table 24-18 in section 24.0 electrical characteristics ). if a slower frequency is desired, the pwm input clock prescaler (divider) select bits (pclkdiv<2:0>) should be used. to achieve 1.04 ns pwm resolution, the auxiliary clock must use the 16x auxiliary pll (apll). all other clock sources will have a minimum pwm resolution of 8 ns. if the primary pll is used as a source for the auxiliary clock, the primary pll should be config- ured up to a maximum operation of 30 mips or less 8.3 reference clock generation the reference clock output logic provides the user with the ability to output a clock signal based on the system clock or the crystal oscillator on a device pin. the user application can specify a wide range of clock scaling prior to outputting the reference clock. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 139 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 8.4 oscillator control registers register 8-1: osccon: os cillator control register ( 1 , 2 ) u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y cosc2 cosc1 cosc0 n o s c 2 ( 3 ) nosc1 ( 3 ) nosc0 ( 3 ) bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/c-0 u-0 u-0 r/w-0 clklock iolock lock c f oswen bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = reserved 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with pll 000 = fast rc oscillator (frc) bit 11 unimplemented: read as 0 bit 10-8 nosc<2:0>: new oscillator selection bits ( 3 ) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = reserved 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with pll 000 = fast rc oscillator (frc) bit 7 clklock: clock lock enable bit if clock switching is enabled and fscm is disabled, (fosc dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 140 ? 2008-2014 microchip technology inc. bit 3 cf: clock fail detect bit (read/clear by application) 1 = fscm has detected clock failure 0 = fscm has not detected clock failure bit 2-1 unimplemented: read as 0 bit 0 oswen: oscillator switch enable bit 1 = request oscillator switch to selection specified by nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: os cillator control register ( 1 , 2 ) (continued) note 1: writes to this register require an unlock sequence. refer to oscillator (part iv) (ds70307) in the ?dspic33f/pic24h family reference manual? (available from the microchip web site) for details. 2: this register is reset only on a power-on reset (por). 3: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switc h to frc mode as a transition clock source between the two pll modes. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 141 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 8-2: clkdiv: clock divisor register ( 1 ) r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 roi doze2 doze1 doze0 dozen ( 2 ) frcdiv2 frcdiv1 frcdiv0 bit 15 bit 8 r/w-0 r/w-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pllpost1 pllpost0 pllpre4 pllpre3 pllpre2 pllpre1 pllpre0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts will clear the dozen bit and the processor clock/peripheral clock ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits 111 = f cy /128 110 = f cy /64 101 = f cy /32 100 = f cy /16 011 = f cy /8 (default) 010 = f cy /4 001 = f cy /2 000 = f cy /1 bit 11 dozen: doze mode enable bit ( 2 ) 1 = doze<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock/peripheral clock ratio forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc oscillator postscaler bits 111 = frc divide-by-256 110 = frc divide-by-64 101 = frc divide-by-32 100 = frc divide-by-16 011 = frc divide-by-8 010 = frc divide-by-4 001 = frc divide-by-2 000 = frc divide-by-1 (default) bit 7-6 pllpost<1:0>: pll vco output divider select bits (also denoted as n2, pll postscaler) 11 = output/8 10 = reserved 01 = output/4 (default) 00 = output/2 bit 5 unimplemented: read as 0 bit 4-0 pllpre<4:0>: pll phase detector input divider bits (also denoted as n1, pll prescaler) 11111 = input/33 00001 = input/3 00000 = input/2 (default) note 1: this register is reset only on a power-on reset (por). 2: this bit is cleared when the roi bit is set and an interrupt occurs. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 142 ? 2008-2014 microchip technology inc. register 8-3: pllfbd: pll feedback divisor register ( 1 ) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 p l l d i v < 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 plldiv<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as 0 bit 8-0 plldiv<8:0>: pll feedback divisor bits (also denoted as m, pll multiplier) 111111111 = 513 000110000 = 50 (default) 000000010 = 4 000000001 = 3 000000000 = 2 note 1: this register is reset only on a power-on reset (por). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 143 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 8-4: osctun: frc oscillator tuning register ( 1 ) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tun<5:0> ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 tun<5:0>: frc oscillator tuning bits ( 2 ) 011111 = center frequency + 11.6% (8.2268 mhz) 011110 = center frequency + 11.2% (8.1992 mhz) 000001 = center frequency + 0.375% (7.3976 mhz) 000000 = center frequency (7.37 mhz nominal) 111111 = center frequency C 0.375% (7.2594 mhz) 100001 = center frequency C 11.6% (6.5132 mhz) 000000 = center frequency C 12% (6.4856 mhz) note 1: this register is reset only on a power-on reset (por). 2: osctun functionality has been provided to help customers compensate for temperature effects on the frc frequency over a wide range of temperatures. the tuning step-size is an approximation and is neither characterized nor tested. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 144 ? 2008-2014 microchip technology inc. register 8-5: aclkcon: auxiliary clock divisor control register ( 1 ) r/w-0 r-0 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 enapll apllck selaclk apstsclr2 apstsclr1 apstsclr0 bit 15 bit 0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 asrcsel frcsel bit 7 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 enapll: auxiliary pll enable bit 1 = apll is enabled 0 = apll is disabled bit 14 apllck: apll locked status bit (read-only) 1 = indicates that auxiliary pll is in lock 0 = indicates that auxiliary pll is not in lock bit 13 selaclk: select auxiliary clock source for auxiliary clock divider bit 1 = auxiliary oscillators provides the source clock for auxiliary clock divider 0 = primary pll (f vco ) provides the source clock for auxiliary clock divider bit 12-11 unimplemented: read as 0 bit 10-8 apstsclr<2:0>: auxiliary clock output divider bits 111 = divided by 1 110 = divided by 2 101 = divided by 4 100 = divided by 8 011 = divided by 16 010 = divided by 32 001 = divided by 64 000 = divided by 256 bit 7 asrcsel: select reference clock source for auxiliary clock bit 1 = primary oscillator is the clock source 0 = no clock input is selected bit 6 frcsel: select reference clock source for auxiliary pll bit 1 = select frc clock for auxiliary pll 0 = input clock source is determined by asrcsel bit setting bit 5-0 unimplemented: read as 0 note 1: this register is reset only on a power-on reset (por). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 145 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 8-6: refocon: reference oscillator control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 roon rosslp rosel rodiv3 ( 1 ) rodiv2 ( 1 ) rodiv1 ( 1 ) rodiv0 ( 1 ) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 roon: reference oscillator output enable bit 1 = reference oscillator output is enabled on the refclk0 pin ( 2 ) 0 = reference oscillator output is disabled bit 14 unimplemented: read as 0 bit 13 rosslp: reference oscillator run in sleep bit 1 = reference oscillator output continues to run in sleep 0 = reference oscillator output is disabled in sleep bit 12 rosel: reference oscillator source select bit 1 = oscillator crystal is used as the reference clock 0 = system clock is used as the reference clock bit 11-8 rodiv<3:0>: reference oscillator divider bits ( 1 ) 1111 = reference clock divided by 32,768 1110 = reference clock divided by 16,384 1101 = reference clock divided by 8,192 1100 = reference clock divided by 4,096 1011 = reference clock divided by 2,048 1010 = reference clock divided by 1,024 1001 = reference clock divided by 512 1000 = reference clock divided by 256 0111 = reference clock divided by 128 0110 = reference clock divided by 64 0101 = reference clock divided by 32 0100 = reference clock divided by 16 0011 = reference clock divided by 8 0010 = reference clock divided by 4 0001 = reference clock divided by 2 0000 = reference clock bit 7-0 unimplemented: read as 0 note 1: the reference oscillator output must be disabled (roon = 0 ) before writing to these bits. 2: this pin is remappable. refer to section 10.6 peripheral pin select for more information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 146 ? 2008-2014 microchip technology inc. 8.5 clock switching operation users can switch applications among any of the four clock sources (primary, lp, frc and lprc) under software control at any time. to limit the possible side effects of this flexibility, dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices have a safeguard lock built into the switch process. 8.5.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in the configuration register must be programmed to 0 . (refer to section 21.1 configuration bits for further details.) if the fcksm1 configuration bit is unprogrammed ( 1 ), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the nosc<2:0> control bits (osccon<10:8>) do not control the clock selection when clock switching is disabled. however, the cosc<2:0> bits (osccon<14:12>) reflect the clock source selected by the fnoscx configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled. it is held at 0 at all times. 8.5.2 oscillator switching sequence to perform a clock switch, the following basic sequence is required: 1. if required, read the cosc<2:0> bits to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the nosc<2:0> control bits for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit to initiate the oscillator switch. after the basic sequence is completed, the system clock hardware responds as follows: 1. the clock switching hardware compares the cosc<2:0> status bits with the new value of the nosc<2:0> control bits. if they are the same, the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock (osccon<5>) and the cf (osccon<3>) status bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware waits until the oscillator start-up timer (ost) expires. if the new source is using the pll, the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the nosc<2:0> bit values are transferred to the cosc<2:0> status bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm are enabled). 8.6 fail-safe clock monitor (fscm) the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by programming. if the fscm function is enabled, the lprc internal oscillator runs at all times (except during sleep mode) and is not subject to control by the watchdog timer. during an oscillator failure, the fscm generates a clock failure trap event and switches the system clock over to the frc oscillator. then, the application program can either attempt to restart the oscillator or execute a controlled shutdown. the trap can be treated as a warm reset by simply loading the reset address into the oscillator fail trap vector. if the pll multiplier is used to scale the system clock, the internal frc is also multiplied by the same factor on clock failure. essentially, the device switches to frc with pll on a clock failure. note: primary oscillator mode has three different submodes (xt, hs and ec), which are determined by the poscmd<1:0> configuration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. note 1: the processor continues to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any pri- mary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direc- tion. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. 3: refer to oscillator (part iv) (ds70307) in the ?dspic33f/pic24h family reference manual? for details. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 147 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 9.0 power-saving features the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices provide the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices can manage power consumption in four different ways: clock frequency instruction-based sleep and idle modes software-controlled doze mode selective peripheral control in software combinations of these methods can be used to selectively tailor an applications power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 clock frequency and clock switching the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices allow a wide range of clock frequencies to be selected under application control. if the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the nosc<2:0> bits (osccon<10:8>). the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 8.0 oscillator configuration . 9.2 instruction-based power-saving modes the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution. idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. the assembler syntax of the pwrsav instruction is shown in example 9-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake-up. 9.2.1 sleep mode the following occur in sleep mode: the system clock source is shut down. if an on-chip oscillator is used, it is turned off the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current the fail-safe clock monitor does not operate, since the system clock source is disabled the lprc clock continues to run in sleep mode if the wdt is enabled the wdt, if enabled, is automatically cleared prior to entering sleep mode some device features or peripherals may continue to operate. this includes the items such as the input change notification on the i/o ports or peripherals that use an external clock input. any peripheral that requires the system clock source for its operation is disabled the device will wake-up from sleep mode on any of these events: any interrupt source that is individually enabled any form of device reset a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source that was active when sleep mode was entered. example 9-1: pwrsav instruction syntax note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to watchdog timer and power-saving modes (ds70196) in the ?dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: sleep_mode and idle_mode are constants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 148 ? 2008-2014 microchip technology inc. 9.2.2 idle mode the following occur in idle mode: the cpu stops executing instructions the wdt is automatically cleared the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 9.4 peripheral module disable ). if the wdt or fscm is enabled, the lprc also remains active the device will wake-up from idle mode on any of these events: any interrupt that is individually enabled any device reset a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the pwrsav instruction, or the first instruction in the isr. 9.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode has completed. the device then wakes up from sleep or idle mode. 9.3 doze mode the preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. in some circumstances, this may not be practical. for example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configura- tions, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. for example, suppose the device is operating at 20 mips and the can module has been configured for 500 kbps based on this device operating speed. if the device is placed in doze mode with a clock frequency ratio of 1:4, the can module continues to communicate at the required bit rate of 500 kbps, but the cpu now starts executing instructions at a frequency of 5 mips. 9.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabled using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. a peripheral module is enabled only if both the associated bit in the pmd register is cleared and the peripheral is supported by the specific dspic ? dsc variant. if the peripheral is present in the device, it is enabled in the pmd register by default. note: if a pmd bit is set, the corresponding module is disabled after a delay of one instruction cycle. similarly, if a pmd bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 149 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 9-1: pmd1: peripheral mo dule disable control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 t3md t2md t1md p w m m d ( 1 ) bit 15 bit 8 r/w-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 i2c1md u 1 m d spi1md adcmd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 t3md : timer3 module disable bit 1 = timer3 module is disabled 0 = timer3 module is enabled bit 12 t2md : timer2 module disable bit 1 = timer2 module is disabled 0 = timer2 module is enabled bit 11 t1md : timer1 module disable bit 1 = timer1 module is disabled 0 = timer1 module is enabled bit 10 unimplemented: read as 0 bit 9 pwmmd : pwm module disable bit ( 1 ) 1 = pwm module is disabled 0 = pwm module is enabled bit 8 unimplemented: read as 0 bit 7 i2c1md : i2c1 module disable bit 1 = i2c1 module is disabled 0 = i2c1 module is enabled bit 6 unimplemented: read as 0 bit 5 u1md : uart1 module disable bit 1 = uart1 module is disabled 0 = uart1 module is enabled bit 4 unimplemented: read as 0 bit 3 spi1md : spi1 module disable bit 1 = spi1 module is disabled 0 = spi1 module is enabled bit 2-1 unimplemented: read as 0 bit 0 adcmd : adc module disable bit 1 = adc module is disabled 0 = adc module is enabled note 1: once the pwm module is re-enabled (pwmmd is set to 1 and then set to 0 ), all pwm registers must be reinitialized. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 150 ? 2008-2014 microchip technology inc. register 9-2: pmd2: peripheral mo dule disable control register 2 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 i c 2 m di c 1 m d bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 o c 2 m do c 1 m d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9 ic2md : input capture 2 module disable bit 1 = input capture 2 module is disabled 0 = input capture 2 module is enabled bit 8 ic1md : input capture 1 module disable bit 1 = input capture 1 module is disabled 0 = input capture 1 module is enabled bit 7-2 unimplemented: read as 0 bit 1 oc2md : output compare 2 module disable bit 1 = output compare 2 module is disabled 0 = output compare 2 module is enabled bit 0 oc1md : output compare 1 module disable bit 1 = output compare 1 module is disabled 0 = output compare 1 module is enabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 151 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 9-3: pmd3: peripheral mo dule disable control register 3 register 9-4: pmd4: peripheral mo dule disable control register 4 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 c m p m d bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10 cmpmd : analog comparator module disable bit 1 = analog comparator module is disabled 0 = analog comparator module is enabled bit 9-0 unimplemented: read as 0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 r e f o m d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as 0 bit 3 refomd : reference clock generator module disable bit 1 = reference clock generator module is disabled 0 = reference clock generator module is enabled bit 2-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 152 ? 2008-2014 microchip technology inc. register 9-5: pmd6: peripheral mo dule disable control register 6 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 pwm4md pwm3md pwm2md pwm1md bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11 pwm4md : pwm generator 4 module disable bit 1 = pwm generator 4 module is disabled 0 = pwm generator 4 module is enabled bit 10 pwm3md : pwm generator 3 module disable bit 1 = pwm generator 3 module is disabled 0 = pwm generator 3 module is enabled bit 9 pwm2md : pwm generator 2 module disable bit 1 = pwm generator 2 module is disabled 0 = pwm generator 2 module is enabled bit 8 pwm1md : pwm generator 1 module disable bit 1 = pwm generator 1 module is disabled 0 = pwm generator 1 module is enabled bit 7-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 153 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 9-6: pmd7: peripheral mo dule disable control register 7 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cmp4md cmp3md cmp2md cmp1md bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11 cmp4md : analog comparator 4 module disable bit 1 = analog comparator 4 module is disabled 0 = analog comparator 4 module is enabled bit 10 cmp3md : analog comparator 3 module disable bit 1 = analog comparator 3 module is disabled 0 = analog comparator 3 module is enabled bit 9 cmp2md : analog comparator 2 module disable bit 1 = analog comparator 2 module is disabled 0 = analog comparator 2 module is enabled bit 8 cmp1md : analog comparator 1 module disable bit 1 = analog comparator 1 module is disabled 0 = analog comparator 1 module is enabled bit 7-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 154 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 155 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 10.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared among the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 10.1 parallel i/o (pio) ports generally a parallel i/o port that shares a pin with a peripheral is subservient to the peripheral. the peripherals output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents loop through, in which a ports digital output can drive the input of a peripheral that shares the same pin. figure 10-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have three regist ers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an out- put. if the data direction bit is 1 , then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write the latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. any bit and its associated data and control registers that are not valid for a particular device will be disabled. that means the corresponding latx and trisx registers and the port pin will read as zeros. when a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. figure 10-1: block diag ram of a typical shared port structure note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to i/o ports (ds70193) in the ?dspic33f/pic24h family reference manual? , which is available on microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 10 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 156 ? 2008-2014 microchip technology inc. 10.2 open-drain configuration in addition to the portx, latx and trisx registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of outputs higher than v dd (for example, 5v) on any desired 5v tolerant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. refer to pin diagrams for the available pins and their functionality. 10.3 configuring analog port pins the adpcfg and trisx registers control the opera- tion of the analog-to-digital (a/d) port pins. the port pins that are to function as analog inputs must have their corresponding trisx bit set (input). if the trisx bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the adpcfg register has a default value of 0x0000; therefore, all pins that share anx functions are analog (not digital) by default. when the portx register is read, all pins configured as analog input channels will read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 10.4 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically, this instruction would be a nop . an example is shown in example 10-1 . 10.5 input change notification the input change notification (icn) function of the i/o ports allows the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices to generate interrupt requests to the processor in response to a change-of-state (cos) on selected input pins. this feature can detect input change-of-states even in sleep mode, when the clocks are disabled. depending on the device pin count, up to 30 external signals (cnx pin) can be selected (enabled) for generating an interrupt request on a change-of-state. four control registers are associated with the cn module. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up connected to it. the pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when the push button or keypad devices are connected. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. setting any of the control bits enables the weak pull-ups for the corresponding pins. equation 10-1: port write/read example note: pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 157 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 10.6 peripheral pin select peripheral pin select configuration enables peripheral set selection and placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature operates over a fixed subset of digital i/o pins. programmers can independently map the input and/or output of most digital peripherals to any one of these i/o pins. peripheral pin select is performed in software, and gen- erally does not require the device to be reprogrammed. hardware safeguards are included that prevent acciden- tal or spurious changes to the peripheral mapping, once it has been established. 10.6.1 available pins the peripheral pin select feature is used with a range of up to 30 pins. the number of available pins depends on the particular device and its pin count. pins that support the peripheral pin select feature include the designation rpn in their full pin designation, where rp designates a remappable peripheral and n is the remappable pin number. 10.6.2 controlling peripheral pin select peripheral pin select features are controlled through two sets of special function registers: one to map peripheral inputs and another one to map outputs. because they are separately controlled, a particular peripherals input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. 10.6.2.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 10-1 through register 10-14 ). each register contains sets of 6-bit fields, with each set associated with one of the remappable peripherals. programming a given peripherals bit field with an appropriate 6-bit value maps the rpn pin with that value to that peripheral. for any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. figure 10-2 illustrates remappable pin selection for u1rx input. figure 10-2: remappable mux input for u1rx note: for input mapping only, the peripheral pin select (pps) functionality does not have priority over the trisx settings. there- fore, when configuring the rpx pin for input, the corresponding bit in the trisx register must also be configured for input (i.e., set to 1 ). rp0 rp1 rp2 rp33 0 33 12 u1rx input u1rxr<5:0> to peripheral downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 158 ? 2008-2014 microchip technology inc. table 10-1: selectable input sources (maps input to function) input name function name register configuration bits external interrupt 1 int1 rpinr0 int1r<5:0> external interrupt 2 int2 rpinr1 int2r<5:0> timer1 external clock t1ck rpinr2 t1ckr<5:0> timer2 external clock t2ck rpinr3 t2ckr<5:0> timer3 external clock t3ck rpinr3 t3ckr<5:0> input capture 1 ic1 rpinr7 ic1r<5:0> input capture 2 ic2 rpinr7 ic2r<5:0> output compare fault a ocfa rpinr11 ocfar<5:0> uart1 receive u1rx rpinr18 u1rxr<5:0> uart1 clear-to-send u1cts rpinr18 u1ctsr<5:0> spi data input 1 sdi1 rpinr20 sdi1r<5:0> spi clock input 1 sck1 rpinr20 sck1r<5:0> spi slave select input 1 ss1 rpinr21 ss1r<5:0> pwm fault input pwm1 flt1 rpinr29 flt1r<5:0> pwm fault input pwm2 flt2 rpinr30 flt2r<5:0> pwm fault input pwm3 flt3 rpinr30 flt3r<5:0> pwm fault input pwm4 flt4 rpinr31 flt4r<5:0> pwm fault input pwm5 flt5 rpinr31 flt5r<5:0> pwm fault input pwm6 flt6 rpinr32 flt6r<5:0> pwm fault input pwm7 flt7 rpinr32 flt7r<5:0> pwm fault input pwm8 flt8 rpinr33 flt8r<5:0> external synchronization signal to pwm master time base synci1 rpinr33 synci1r<5:0> external synchronization signal to pwm master time base synci2 rpinr34 synci2r<5:0> downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 159 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 10.6.2.2 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. like the rpinrx registers, each register contains sets of 6-bit fields, with each set associated with one rpn pin (see register 10-15 through register 10-31 ). the value of the bit field corresponds to one of the peripherals, and that peripherals output is mapped to the pin (see table 10-2 and figure 10-3 ). the list of peripherals for output mapping also includes a null value of 00000 because of the mapping technique. this permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. figure 10-3: multiplexing of remappable output for rpn table 10-2: output selection for remappable pin (rpn) 0 45 3 rporn<5:0> default u1tx output enable u1rts output enable 4 pwm4l output enable 19 oc2 output enable 0 45 3 default u1tx output u1rts output 4 pwm4l output 19 oc2 output output enable output data rpn function rporn<5:0> output name null 000000 rpn tied to default port pin u1tx 000011 rpn tied to uart1 transmit u1rts 000100 rpn tied to uart1 ready-to-send sdo1 000111 rpn tied to spi1 data output sck1 001000 rpn tied to spi1 clock output ss1 001001 rpn tied to spi1 slave select output oc1 010010 rpn tied to output compare 1 oc2 010011 rpn tied to output compare 2 synco1 100101 rpn tied to external device synchronization signal via pwm master time base refclko 100110 refclk output signal acmp1 100111 rpn tied to analog comparator output 1 acmp2 101000 rpn tied to analog comparator output 2 acmp3 101001 rpn tied to analog comparator output 3 acmp4 101010 rpn tied to analog comparator output 4 pwm4h 101100 rpn tied to pwm output pins associated with pwm generator 4 pwm4l 101101 rpn tied to pwm output pins associated with pwm generator 4 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 160 ? 2008-2014 microchip technology inc. 10.6.2.3 virtual pins dspic33fj06gs101/x02 a nd dspic33fj16gsx02/x04 devices support four virtual rpn pins (rp32, rp33, rp34 and rp35), which are identical in functionality to all other rpn pins, with the exception of pinouts. these four pins are internal to the devices and are not connected to a physical device pin. these pins provide a simple way for inter-peripheral connection without utilizing a physical pin. for example, the output of the analog comparator can be connected to rp32 and the pwm fault input can be configured for rp32 as well. this configuration allows the analog comparator to trigger pwm faults without the use of an actual physical pin on the device. 10.6.3 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dspic33f devices include three features to prevent alterations to the peripheral map: control register lock sequence continuous state monitoring configuration bit pin select lock 10.6.3.1 control register lock under normal operation, writes to the rpinrx and rporx registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is controlled by the iolock bit (osccon<6>). setting iolock prevents writes to the control registers; clearing iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 0x46 to osccon<7:0>. 2. write 0x57 to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillators lock bit, iolock remains in one state until changed. this allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 10.6.3.2 continuous state monitoring in addition to being protected from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset will be triggered. 10.6.3.3 configuration bit pin select lock as an additional level of safety, the device can be configured to prevent many write session to the rpinrx and rporx registers. the iol1way (fosc<5>) configuration bit blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure will not execute and the peripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one write session. programming iol1way allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. note: mplab ? c30 provides built-in c language functions for unlocking the osccon register: __builtin_write_oscconl(value) __builtin_write_oscconh(value) see the mplab c30 help files for more information. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 161 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 10.7 peripheral pin select registers dspic33fj06gs101/x02 a nd dspic33fj16gsx02/x04 families of devices implement 34 registers for remappable peripheral configuration: 15 input remappable peripheral registers 17 output remappable peripheral registers not all output remappable peripheral registers are implemented on all devices. see the specific register description for further details. note: input and output register values can only be changed if osccon dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 162 ? 2008-2014 microchip technology inc. register 10-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 int2r5 int2r4 int2r3 int2r2 int2r1 int2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 int2r<5:0>: assign external interrupt 2 (intr2) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 163 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-3: rpinr3: peripheral pin select input register 3 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 t3ckr5 t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 t2ckr5 t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 t3ckr<5:0>: assign timer3 external clock (t3ck) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 t2ckr<5:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 164 ? 2008-2014 microchip technology inc. register 10-4: rpinr7: peripheral pin select input register 7 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ic2r5 ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ic1r5 ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 ic2r<5:0>: assign input capture 2 (ic2) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 ic1r<5:0>: assign input capture 1 (ic1) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 165 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-5: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ocfar5 ocfar4 ocfar3 ocfar2 ocfar1 ocfar0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 ocfar<5:0>: assign output capture a (ocfa) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 166 ? 2008-2014 microchip technology inc. register 10-6: rpinr18: peripheral pin select input register 18 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u1ctsr5 u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u1rxr5 u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 u1ctsr<5:0>: assign uart1 clear-to-send (u1cts ) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 u1rxr<5:0>: assign uart1 receive (u1rx) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 167 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-7: rpinr20: peripheral pin select input register 20 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 sck1r5 sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 sdi1r5 sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 sck1r<5:0>: assign spi1 clock input (sck1in) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 sdi1r<5:0>: assign spi1 data input (sdi1) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 168 ? 2008-2014 microchip technology inc. register 10-8: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ss1r5 ss1r4 ss1r3 ss1r2 ss1r1 ss1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 ss1r<5:0>: assign spi1 slave select input (ss1in) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 169 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-9: rpinr29: peripheral pin select input register 29 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt1r5 flt1r4 flt1r3 flt1r2 flt1r1 flt1r0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 flt1r<5:0>: assign pwm fault input 1 (flt1) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 170 ? 2008-2014 microchip technology inc. register 10-10: rpinr30: peripheral pin select input register 30 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt3r5 flt3r4 flt3r3 flt3r2 flt3r1 flt3r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt2r5 flt2r4 flt2r3 flt2r2 flt2r1 flt2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 flt3r<5:0>: assign pwm fault input 3 (flt3) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 flt2r<5:0>: assign pwm fault input 2 (flt2) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 171 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-11: rpinr31: peripheral pin select input register 31 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt5r5 flt5r4 flt5r3 flt5r2 flt5r1 flt5r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt4r5 flt4r4 flt4r3 flt4r2 flt4r1 flt4r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 flt5r<5:0>: assign pwm fault input 5 (flt5) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 flt4r<5:0>: assign pwm fault input 4 (flt4) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 172 ? 2008-2014 microchip technology inc. register 10-12: rpinr32: peripheral pin select input register 32 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt7r5 flt7r4 flt7r3 flt7r2 flt7r1 flt7r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt6r5 flt6r4 flt6r3 flt6r2 flt6r1 flt6r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 flt7r<5:0>: assign pwm fault input 7 (flt7) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 flt6r<5:0>: assign pwm fault input 6 (flt6) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 173 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-13: rpinr33: peripheral pin select input register 33 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 synci1r5 synci1r4 synci1r3 synci1r2 synci1r1 synci1r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flt8r5 flt8r4 flt8r3 flt8r2 flt8r1 flt8r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 synci1r<5:0>: assign pwm master time base external synchronization signal to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 bit 7-6 unimplemented: read as 0 bit 5-0 flt8r<5:0>: assign pwm fault input 8 (flt8) to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 174 ? 2008-2014 microchip technology inc. register 10-14: rpinr34: peripheral pin select input register 34 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 synci2r5 synci2r4 synci2r3 synci2r2 synci2r1 synci2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 synci2r<5:0>: assign pwm master time base external synchronization signal to the corresponding rpn pin bits 111111 = input tied to v ss 100011 = input tied to rp35 100010 = input tied to rp34 100001 = input tied to rp33 100000 = input tied to rp32 00000 = input tied to rp0 register 10-15: rpor0: peripheral pin select output register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp1r5 rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp0r5 rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp1r<5:0>: peripheral output function is assigned to rp1 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp0r<5:0>: peripheral output function is assigned to rp0 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 175 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-16: rpor1: peripheral pin select output register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp3r5 rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp2r5 rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp3r<5:0>: peripheral output function is assigned to rp3 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp2r<5:0>: peripheral output function is assigned to rp2 output pin bits (see table 10-2 for peripheral function numbers) register 10-17: rpor2: peripheral pin select output register 2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp5r5 rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp4r5 rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp5r<5:0>: peripheral output function is assigned to rp5 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp4r<5:0>: peripheral output function is assigned to rp4 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 176 ? 2008-2014 microchip technology inc. register 10-18: rpor3: peripheral pin select output register 3 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp7r5 rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp6r5 rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp7r<5:0>: peripheral output function is assigned to rp7 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp6r<5:0>: peripheral output function is assigned to rp6 output pin bits (see table 10-2 for peripheral function numbers) register 10-19: rpor4: peripheral pin select output register 4 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp9r5 rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp8r5 rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp9r<5:0>: peripheral output function is assigned to rp9 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp8r<5:0>: peripheral output function is assigned to rp8 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is not implemented in the dspic33fj06gs101 device. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 177 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-20: rpor5: peripheral pin select output register 5 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp11r5 rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp10r5 rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp11r<5:0>: peripheral output function is assigned to rp11 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp10r<5:0>: peripheral output function is assigned to rp10 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is not implemented in the dspic33fj06gs101 device. register 10-21: rpor6: peripheral pin select output register 6 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp13r5 rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp12r5 rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp13r<5:0>: peripheral output function is assigned to rp13 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp12r<5:0>: peripheral output function is assigned to rp12 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is not implemented in the dspic33fj06gs101 device. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 178 ? 2008-2014 microchip technology inc. register 10-22: rpor7: peripheral pin select output register 7 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp15r5 rp15r4 rp15r3 rp15r2 rp15r1 rp15r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp14r5 rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp15r<5:0>: peripheral output function is assigned to rp15 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp14r<5:0>: peripheral output function is assigned to rp14 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is not implemented in the dspic33fj06gs101 device. register 10-23: rpor8: peripheral pin select output register 8 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp17r5 rp17r4 rp17r3 rp17r2 rp17r1 rp17r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp16r5 rp16r4 rp16r3 rp16r2 rp16r1 rp16r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp17r<5:0>: peripheral output function is assigned to rp17 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp16r<5:0>: peripheral output function is assigned to rp16 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 179 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-24: rpor9: peripheral pin select output register 9 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp19r5 rp19r4 rp19r3 rp19r2 rp19r1 rp19r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp18r5 rp18r4 rp18r3 rp18r2 rp18r1 rp18r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp19r<5:0>: peripheral output function is assigned to rp19 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp18r<5:0>: peripheral output function is assigned to rp18 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. register 10-25: rpor10: peripheral pin select output register 10 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp21r5 rp21r4 rp21r3 rp21r2 rp21r1 rp21r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp20r5 rp20r4 rp20r3 rp20r2 rp20r1 rp20r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp21r<5:0>: peripheral output function is assigned to rp21 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp20r<5:0>: peripheral output function is assigned to rp20 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 180 ? 2008-2014 microchip technology inc. register 10-26: rpor11: peripheral pin select output register 11 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp23r5 rp23r4 rp23r3 rp23r2 rp23r1 rp23r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp22r5 rp22r4 rp22r3 rp22r2 rp22r1 rp22r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp23r<5:0>: peripheral output function is assigned to rp23 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp22r<5:0>: peripheral output function is assigned to rp22 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. register 10-27: rpor12: peripheral pin select output register 12 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp25r5 rp25r4 rp25r3 rp25r2 rp25r1 rp25r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp24r5 rp24r4 rp24r3 rp24r2 rp24r1 rp24r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp25r<5:0>: peripheral output function is assigned to rp25 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp24r<5:0>: peripheral output function is assigned to rp24 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 181 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 10-28: rpor13: peripheral pin select output register 13 ( 1 ) register 10-29: rpor14: peripheral pin select output register 14 ( 1 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp27r5 rp27r4 rp27r3 rp27r2 rp27r1 rp27r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp26r5 rp26r4 rp26r3 rp26r2 rp26r1 rp26r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp27r<5:0>: peripheral output function is assigned to rp27 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp26r<5:0>: peripheral output function is assigned to rp26 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp29r5 rp29r4 rp29r3 rp29r2 rp29r1 rp29r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp28r5 rp28r4 rp28r3 rp28r2 rp28r1 rp28r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp29r<5:0>: peripheral output function is assigned to rp29 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp28r<5:0>: peripheral output function is assigned to rp28 output pin bits (see table 10-2 for peripheral function numbers) note 1: this register is implemented in the dspic33fj16gs404 and dspic33fj16gs504 d evices only. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 182 ? 2008-2014 microchip technology inc. register 10-30: rpor16: peripheral pin select output register 16 register 10-31: rpor17: peripheral pin select output register 17 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp33r5 rp33r4 rp33r3 rp33r2 rp33r1 rp33r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp32r5 rp32r4 rp32r3 rp32r2 rp32r1 rp32r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp33r<5:0>: peripheral output function is assigned to rp33 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp32r<5:0>: peripheral output function is assigned to rp32 output pin bits (see table 10-2 for peripheral function numbers) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp35r5 rp35r4 rp35r3 rp35r2 rp35r1 rp35r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp34r5 rp34r4 rp34r3 rp34r2 rp34r1 rp34r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp35r<5:0>: peripheral output function is assigned to rp35 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp34r<5:0>: peripheral output function is assigned to rp34 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 183 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 11.0 timer1 the timer1 module is a 16-bit timer, which can serve as a time counter for the real-time clock (rtc), or operate as a free-running interval timer/counter. the timer1 module has the following unique features over other timers: can be operated from the low-power 32 khz crystal oscillator available on the device can be operated in asynchronous counter mode from an external clock source optionally, the external clock input (t1ck) can be synchronized to the internal device clock and the clock synchronization is performed after the prescaler the unique features of timer1 allow it to be used for real-time clock (rtc) applications. a block diagram of timer1 is shown in figure 11-1 . the timer1 module can operate in one of the following modes: timer mode gated timer mode synchronous counter mode asynchronous counter mode in timer and gated timer modes, the input clock is derived from the internal instruction cycle clock (f cy ). in synchronous and asynchronous counter modes, the input clock is derived from the external clock input at the t1ck pin. the timer modes are determined by the following bits: timer clock source control bit (tcs): t1con<1> timer synchronization control bit (tsync): t1con<2> timer gate control bit (tgate): t1con<6> the timer control bit settings for different operating modes are given in the table 11-1 . table 11-1: timer mode settings figure 11-1: 16-bit timer1 module block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to timers (ds70205) in the ?dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. mode tcs tgate tsync timer 00x gated timer 01x synchronous counter 1x1 asynchronous counter 1x0 tgate tcs 00 10 x1 tmr1 comparator pr1 tgate set t1if flag 0 1 tsync 1 0 sync equal reset t1ck prescaler (/n) tckps<1:0> gate sync f cy falling edge detect prescaler (/n) tckps<1:0> downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 184 ? 2008-2014 microchip technology inc. register 11-1: t1con: timer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton t s i d l bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate tckps1 tckps0 tsync tcs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as 0 bit 13 tsidl: timer1 stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timer1 gated time accumulation enable bit when t c s = 1 : this bit is ignored. when t c s = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0> timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as 0 bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronizes external clock input 0 = does not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from t1ck pin (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 185 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 12.0 timer2/3 features timer2 is a type b timer that offers the following major features: a type b timer can be concatenated with a type c timer to form a 32-bit timer external clock input (txck) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. figure 12-1 shows a block diagram of the type b timer. timer3 is a type c timer that offers the following major features: a type c timer can be concatenated with a type b timer to form a 32-bit timer the external clock input (txck) is always synchronized to the internal device clock and the clock synchronization is performed before the prescaler a block diagram of the type c timer is shown in figure 12-2 . figure 12-1: type b timer block diagram (x = 2) figure 12-2: type c timer block diagram (x = 3) note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to timers (ds70205) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: timer3 is not available on all devices. prescaler (/n) tgate tcs 00 10 x1 tmrx comparator prx tgate set txif flag 0 1 sync tckps<1:0> equal reset txck gate sync f cy falling edge detect prescaler (/n) tckps<1:0> prescaler (/n) gate sync tgate tcs 00 10 x1 tmrx comparator prx f cy tgate falling edge detect set txif flag 0 1 sync tckps<1:0> equal reset txck prescaler (/n) tckps<1:0> downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 186 ? 2008-2014 microchip technology inc. the timer2/3 module can operate in one of the following modes: timer mode gated timer mode synchronous counter mode in timer and gated timer modes, the input clock is derived from the internal instruction cycle clock (f cy ). in synchronous counter mode, the input clock is derived from the external clock input at the txck pin. the timer modes are determined by the following bits: tcs (txcon<1>): timer clock source control bit tgate (txcon<6>): timer gate control bit timer control bit settings for different operating modes are given in the ta b l e 1 2 - 1 . table 12-1: timer mode settings 12.1 16-bit operation to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer. 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie. use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit. 12.2 32-bit operation a 32-bit timer module can be formed by combining a type b and a type c 16-bit timer module. for 32-bit timer operation, the t32 control bit in the type b timer control (txcon<3>) register must be set. the type c timer holds the most significant word (msw) and the type b timer holds the least significant word (lsw) for 32-bit operation. when configured for 32-bit operation, only the type b timer control (txcon) register bits are required for setup and control while the type c timer control register bits are ignored (except the tsidl bit). for interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority control bits of the type c timer. the interrupt control and status bits for the type b timer are ignored during 32-bit timer operation. the timer2 and timer 3 that can be combined to form a 32-bit timer are listed in table 12-2 . table 12-2: 32-bit timer a block diagram representation of the 32-bit timer module is shown in figure 12-3 . the 32-timer module can operate in one of the following modes: timer mode gated timer mode synchronous counter mode to configure the features of timer2/3 for 32-bit operation: 1. set the t32 control bit. 2. select the prescaler ratio for timer2 using the tckps<1:0> bits. 3. set the clock and gating modes using the corresponding tcs and tgate bits. 4. load the timer period value. pr3 contains the most significant word of the value, while pr2 contains the least significant word. 5. if interrupts are required, set the interrupt enable bit, t3ie. use the priority bits, t3ip<2:0>, to set the interrupt priority. while timer2 controls the timer, the interrupt appears as a timer3 interrupt. 6. set the corresponding ton bit. the timer value at any point is stored in the register pair, tmr3:tmr2, which always contains the most significant word of the count, while tmr2 contains the least significant word. mode tcs tgate timer 00 gated timer 01 synchronous counter 1x type b timer (lsw) type c timer (msw) timer2 timer3 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 187 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 12-3: 32-bit timer block diagram prescaler (/n) tgate tcs 00 10 x1 tmrx (1) prx tgate set tyif 0 1 sync tckps<1:0> equal txck gate sync f cy falling edge detect prescaler (/n) tckps<1:0> tmry (2) comparator pry reset msw lsw tmryhld data bus <15:0> flag note 1: timerx is a type b timer (x = 2). 2: timery is a type c timer (y = 3). downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 188 ? 2008-2014 microchip technology inc. register 12-1: txcon: timerx control register (x = 2) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton t s i d l bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate tckps1 tckps0 t32 t c s bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timerx on bit when t32 = 1 (in 32-bit timer mode): 1 = starts 32-bit tmrx:tmry timer pair 0 = stops 32-bit tmrx:tmry timer pair when t32 = 0 (in 16-bit timer mode): 1 = starts 16-bit timer 0 = stops 16-bit timer bit 14 unimplemented: read as 0 bit 13 tsidl: timerx stop in idle mode bit 1 = discontinues timer operation when device enters idle mode 0 = continues timer operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timerx input clock prescale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 t32: 32-bit timerx mode select bit 1 = tmrx and tmry form a 32-bit timer 0 = tmrx and tmry form a separate 16-bit timer bit 2 unimplemented: read as 0 bit 1 tcs: timerx clock source select bit 1 = external clock from txck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 189 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 12-2: tycon: timery control register (y = 3) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ( 2 ) t s i d l ( 1 ) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 t g a t e ( 2 ) tckps1 ( 2 ) tckps0 ( 2 ) t c s ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timery on bit ( 2 ) 1 = starts 16-bit timer y 0 = stops 16-bit timer y bit 14 unimplemented: read as 0 bit 13 tsidl: timery stop in idle mode bit ( 1 ) 1 = discontinues timer operation when device enters idle mode 0 = continues timer operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timer y gated time accumulation enable bit ( 2 ) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer y input clock prescale select bits ( 2 ) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 unimplemented: read as 0 bit 1 tcs: timer y clock source select bit ( 2 ) 1 = external clock from txck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as 0 note 1: when 32-bit timer operation is enabled (t32 = 1 ) in the timerx control register (txcon<3>), the tsidl bit must be cleared to operate the 32-bit timer in idle mode. 2: when the 32-bit timer operation is enabled (t32 = 1 ) in the timerx control (txcon<3>) register, these bits have no effect. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 190 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 191 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 13.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices support up to two input capture channels. the input capture module captures the 16-bit value of the selected time base register when an event occurs at the icx pin. the events that cause a capture event are listed below in three categories: simple capture event modes: - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin capture timer value on every edge (rising and falling) prescaler capture event modes: - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select one of the two 16-bit timers (timer2 or timer3) for the time base. the selected timer can use either an internal or external clock. other operational features include: device wake-up from capture pin during cpu sleep and idle modes interrupt on input capture event 4-word fifo buffer for capture values - interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled use of input capture to provide additional sources of external interrupts figure 13-1: input capture x block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to input capture (ds70198) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. icxbuf icx pin icm<2:0> (icxcon<2:0>) mode select 3 10 set flag icxif (in ifsx register) tmr2 tmr3 edge detection logic 16 16 fifo r/w logic icxi<1:0> icov, icbne (icxcon<4:3>) icxcon interrupt logic system bus from 16-bit timers ictmr (icxcon<7>) fifo prescaler counter (1, 4, 16) and clock synchronizer note 1: an x in a signal, register or bit nam e denotes the number of the capture channel. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 192 ? 2008-2014 microchip technology inc. 13.1 input capture register register 13-1: icxcon: input capture x control register (x = 1, 2) u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 i c s i d l bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0, hc r-0, hc r/w-0 r/w-0 r/w-0 ictmr ici1 ici0 icov icbne icm2 icm1 icm0 bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 icsidl: input capture module stop in idle control bit 1 = input capture module halts in cpu idle mode 0 = input capture module continues to operate in cpu idle mode bit 12-8 unimplemented: read as 0 bit 7 ictmr: input capture timer select bits 1 = tmr2 contents are captured on a capture event 0 = tmr3 contents are captured on a capture event bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 = input capture functions as interrupt pin only when device is in sleep or idle mode; rising edge detect only, all other control bits are not applicable 110 = unused (module disabled) 101 = capture mode, every 16th rising edge 100 = capture mode, every 4th rising edge 011 = capture mode, every rising edge 010 = capture mode, every falling edge 001 = capture mode, every edge (rising and falling); ici<1:0> bits do not control interrupt generation for this mode 000 = input capture module turned off downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 193 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 14.0 output compare the output compare module can select either timer2 or timer3 for its time base. the module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. the state of the output pin changes when the timer value matches the compare register value. the output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. the output compare module can also generate interrupts on compare match events. the output compare module has multiple operating modes: active-low one-shot mode active-high one-shot mode toggle mode delayed one-shot mode continuous pulse mode pwm mode without fault protection pwm mode with fault protection figure 14-1: output compare x module block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to output compare (ds70005157) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. ocxr comparator output logic ocm<2:0> output enable ocx set flag bit ocxif ocxrs mode select 3 0 1 octsel 0 1 16 16 ocfa tmr2 tmr2 q s r tmr3 tmr3 rollover rollover note: an x in a signal, register or bit name denotes the number of the output compare channels. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 194 ? 2008-2014 microchip technology inc. 14.1 output compare modes configure the output compare modes by setting the appropriate output compare mode (ocm<2:0>) bits in the output compare control (ocxcon<2:0>) register. table 14-1 lists the different bit settings for the output compare modes. figure 14-2 illustrates the output compare operation for various modes. the user application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. table 14-1: output compare modes figure 14-2: output compare operation note: refer to output compare (ds70209) in the ?dspic33f/pic24h family reference manual? for ocxr and ocxrs register restrictions. ocm<2:0> mode ocx pin initial state ocx interrupt generation 111 pwm with fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero ocfa falling edge for oc1 to oc4 110 pwm without fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero no interrupt 101 continuous pulse 0 ocx falling edge 100 delayed one-shot 0 ocx falling edge 011 toggle current output is maintained ocx rising and falling edge 010 active-high one-shot 1 ocx falling edge 001 active-low one-shot 0 ocx rising edge 000 module disabled controlled by gpio register ocxrs tmry ocxr timer is reset on period match continuous pulse (ocm<2:0> = 101 ) pwm (ocm<2:0> = 110 or 111 ) active-low one-shot (ocm<2:0> = 001 ) active-high one-shot (ocm<2:0> = 010 ) toggle (ocm<2:0> = 011 ) delayed one-shot (ocm<2:0> = 100 ) output compare mode enabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 195 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 14-1: ocxcon: output compare x control register (x = 1, 2) u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 o c s i d l bit 15 bit 8 u-0 u-0 u-0 r-0, hc r/w-0 r/w-0 r/w-0 r/w-0 ocflt octsel ocm2 ocm1 ocm0 bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 ocsidl: stop output compare in idle mode control bit 1 = output compare x halts in cpu idle mode 0 = output compare x continues to operate in cpu idle mode bit 12-5 unimplemented: read as 0 bit 4 ocflt: pwm fault condition status bit 1 = pwm fault condition has occurred (cleared in hardware only) 0 = no pwm fault condition has occurred (this bit is only used when ocm<2:0> = 111 ) bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for output compare x 0 = timer2 is the clock source for output compare x bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx, fault pin is enabled 110 = pwm mode on ocx, fault pin is disabled 101 = initializes ocx pin low, generates continuous output pulses on ocx pin 100 = initializes ocx pin low, generates single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initializes ocx pin high, compare event forces ocx pin low 001 = initializes ocx pin low, compare event forces ocx pin high 000 = output compare channel is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 196 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 197 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 15.0 high-speed pwm the high-speed pwm module on the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 devices supports a wide variety of pwm modes and output formats. this pwm module is ideal for power conversion applications, such as: ac/dc converters dc/dc converters power factor correction (pfc) uninterruptible power supply (ups) inverters battery chargers digital lighting 15.1 features overview the high-speed pwm module incorporates the following features: 2-4 pwm generators with 4-8 outputs individual time base and duty cycle for each of the eight pwm outputs dead time for rising and falling edges: duty cycle resolution of 1.04 ns dead-time resolution of 1.04 ns phase-shift resolution of 1.04 ns frequency resolution of 1.04 ns pwm modes supported: - standard edge-aligned - true independent output - complementary - center-aligned - push-pull - multiphase - variable phase - fixed off-time - current reset - current-limit independent fault/current-limit inputs for each of the eight pwm outputs output override control special event trigger pwm capture feature prescaler for input clock dual trigger from pwm to adc pwmxh, pwmxl output pin swapping pwm4h, pwm4l pins remappable on-the-fly pwm frequency, duty cycle and phase-shift changes disabling of individual pwm generators to reduce power consumption leading-edge blanking (leb) functionality figure 15-1 conceptualizes the pwm module in a simplified block diagram. figure 15-2 illustrates how the module hardware is partitioned for each pwm output pair for the complementary pwm mode. each functional unit of the pwm module is discussed in subsequent sections. the pwm module contains four pwm generators. the module has up to eight pwm output pins: pwm1h, pwm1l, pwm2h, pwm2l, pwm3h, pwm3l, pwm4h and pwm4l. for complementary outputs, these eight i/o pins are grouped into h/l pairs. note 1: this data sheet summarizes the fea- tures of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to high- speed pwm (ds70323) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: duty cycle, dead time, phase shift and frequency resolution is 8.32 ns in center-aligned pwm mode. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 198 ? 2008-2014 microchip technology inc. 15.2 feature description the pwm module is designed for applications that require: high-resolution at high pwm frequencies the ability to drive standard, edge-aligned, center-aligned complementary mode, and push-pull mode outputs the ability to create multiphase pwm outputs for center-aligned mode, the duty cycle, period phase and dead-time resolutions will be 8.32 ns. two common, medium power converter topologies are push-pull and half-bridge. these designs require the pwm output signal to be switched between alternate pins, as provided by the push-pull pwm mode. phase-shifted pwm describes the situation where each pwm generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. multiphase pwm is often used to improve dc/dc converter load transient response, and reduce the size of output filter capacitors and inductors. multiple dc/ dc converters are often operated in parallel, but phase-shifted in time. a single pwm output operating at 250 khz has a period of 4 ? s, but an array of four pwm channels, staggered by 1 ? s each, yields an effective switching frequency of 1 mhz. multiphase pwm applications typically use a fixed-phase relationship. variable phase pwm is useful in zero voltage transition (zvt) power converters. here, the pwm duty cycle is always 50%, and the power flow is controlled by varying the relative phase shift between the two pwm generators. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 199 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 15-1: simplified conceptual block diagram of high-speed pwm mux latch comparator timer pdc2 phase mux latch comparator timer pdc3 phase mux latch comparator timer pdc4 phase mux latch comparator timer pdc1 pwmconx lebconx channel 1 dead-time generator ptcon sevtcmp comparator special event ioconx pwm enable and mode control channel 3 dead-time generator channel 4 dead-time generator altdtrx, dtrx dead-time control special event postscaler flt x (1) pwm3l pwm3h pwm2l pwm2h 1 pwm1l pwm1h fclconx pin and mode control mdc adc trigger control master duty cycle register fault mode and pin control pin override control special event ptper timer period pwm gen 1 pwm gen 2 pwm gen 4 ptmr master time base phase pwm gen 3 channel 2 dead-time generator pwm4l (1) pwm4h (1) pwm user, current-limit and fault override and routing logic fault clmt override logic trigger comparison value trgconx control for blanking external input signals synco (1) synci x (1) note 1: these pins are remappable. external time base synchronization downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 200 ? 2008-2014 microchip technology inc. figure 15-2: partitioned output pair, complementary pwm mode 15.3 control registers the following registers control the operation of the high-speed pwm module. ptcon: pwm time base control register ptcon2: pwm clock divider select register ptper: pwm master time base register(1) sevtcmp: pwm special event compare register mdc: pwm master duty cycle register(1,2) pwmconx: pwmx control register pdcx: pwmx generator duty cycle register(1,2) phasex: pwmx primary phase-shift register(1,2) (provides the local time base period for pwmxh) dtrx: pwmx dead-time register altdtrx: pwmx alternate dead-time register sdcx: pwmx secondary duty cycle register(1,2) sphasex: pwmx secondary phase-shift register(1,2) (provides the local time base period for pwmxl) trgconx: pwmx trigger control register ioconx: pwmx i/o control register fclconx: pwmx fault current-limit control register trigx: pwmx primary trigger compare value register strigx: pwmx secondary trigger compare value register lebconx: leading-edge blanking control register(1) pwmcapx: primary pwmx time base capture register pwm duty cycle register duty cycle comparator fault override values channel override values fault pin assignment logic fault pin pwm x h pwm x l tmr < pdc pwm override logic dead-time logic fault active phase offset m u x m u x timer/counter downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 201 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-1: ptcon: pwm time base control register r/w-0 u-0 r/w-0 hs/hc-0 r/w-0 r/w-0 r/w-0 r/w-0 pten ptsidl sestat seien eipu ( 1 ) syncpol ( 1 ) syncoen ( 1 ) bit 15 bit 8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 syncen ( 1 ) syncsrc1 ( 1 ) syncsrc0 ( 1 ) sevtps3 ( 1 ) sevtps2 ( 1 ) sevtps1 ( 1 ) sevtps0 ( 1 ) bit 7 bit 0 legend: hc = hardware clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pten: pwm module enable bit 1 = pwm module is enabled 0 = pwm module is disabled bit 14 unimplemented: read as 0 bit 13 ptsidl: pwm time base stop in idle mode bit 1 = pwm time base halts in cpu idle mode 0 = pwm time base runs in cpu idle mode bit 12 sestat: special event interrupt status bit 1 = special event interrupt is pending 0 = special event interrupt is not pending bit 11 seien: special event interrupt enable bit 1 = special event interrupt is enabled 0 = special event interrupt is disabled bit 10 eipu: enable immediate period updates bit ( 1 ) 1 = active period register is updated immediately 0 = active period register updates occur on pwm cycle boundaries bit 9 syncpol: synchronization input/output polarity bit ( 1 ) 1 = syncix and synco polarity is inverted (active-low) 0 = syncix and synco are active-high bit 8 syncoen: primary time base sync enable bit ( 1 ) 1 = synco output is enabled 0 = synco output is disabled bit 7 syncen: external time base synchronization enable bit ( 1 ) 1 = external synchronization of primary time base is enabled 0 = external synchronization of primary time base is disabled bit 6 unimplemented: read as 0 bit 5-4 syncsrc<1:0>: synchronous source selection bits ( 1 ) 11 = reserved 10 = reserved 01 = synci2 00 = synci1 note 1: these bits should be changed only when pten = 0 . in addition, when using the syncix feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 202 ? 2008-2014 microchip technology inc. bit 3-0 sevtps<3:0>: pwm special event trigger output postscaler select bits ( 1 ) 1111 = 1:16 postscaler generates a special event trigger trigger on every sixteenth compare match event 0001 = 1:2 postscaler generates a special event trigger on every second compare match event 0000 = 1:1 postscaler generates a special event trigger on every compare match event register 15-1: ptcon: pwm time base control register (continued) note 1: these bits should be changed only when pten = 0 . in addition, when using the syncix feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 203 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-2: ptcon2: pwm cl ock divider select register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 p c l k d i v < 2 : 0 > ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 pclkdiv<2:0>: pwm input clock prescaler (divider) select bits ( 1 ) 111 = reserved 110 = divide-by-64, maximum pwm timing resolution 101 = divide-by-32, maximum pwm timing resolution 100 = divide-by-16, maximum pwm timing resolution 011 = divide-by-8, maximum pwm timing resolution 010 = divide-by-4, maximum pwm timing resolution 001 = divide-by-2, maximum pwm timing resolution 000 = divide-by-1, maximum pwm timing resolution (power-on default) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. register 15-3: ptper: pwm master time base register ( 1 ) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ptper <15:8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 ptper <7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 ptper<15:0>: pwm master time base (pmtmr) period value bits note 1: the minimum value that can be loaded into the ptper register is 0x0010 and the maximum value is 0xfff8. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 204 ? 2008-2014 microchip technology inc. register 15-4: sevtcmp: pwm special event compare register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtcmp <15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 sevtcmp <7:3> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 sevtcmp<12:0> : special event compare count value bits bit 2-0 unimplemented: read as 0 register 15-5: mdc: pwm ma ster duty cycle register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mdc<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mdc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 mdc<15:0>: master pwm duty cycle value bits note 1: the smallest pulse width that can be generated on the pwm output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of period C 0x0008. 2: as the duty cycle gets closer to 0% or 100% of the pwm period (0 ns-40 ns, depending on the mode of operation), the pwm duty cycle resolution will degrade from 1 lsb to 3 lsbs. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 205 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-6: pwmconx: pwmx control register hs/hc-0 hs/hc-0 hs/hc-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fltstat ( 1 ) clstat ( 1 ) trgstat fltien clien trgien itb ( 3 ) mdcs ( 3 ) bit 15 bit 8 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 dtc1 dtc0 c a m ( 2 , 3 ) xpres ( 4 ) iue bit 7 bit 0 legend: hc = hardware clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 fltstat: fault interrupt status bit ( 1 ) 1 = fault interrupt is pending 0 = no fault interrupt is pending; this bit is cleared by setting fltien = 0 bit 14 clstat: current-limit interrupt status bit ( 1 ) 1 = current-limit interrupt is pending 0 = no current-limit interrupt is pending; this bit is cleared by setting clien = 0 bit 13 trgstat: trigger interrupt status bit 1 = trigger interrupt is pending 0 = no trigger interrupt is pending; this bit is cleared by setting trgien = 0 bit 12 fltien: fault interrupt enable bit 1 = fault interrupt is enabled 0 = fault interrupt is disabled and the fltstat bit is cleared bit 11 clien: current-limit interrupt enable bit 1 = current-limit interrupt is enabled 0 = current-limit interrupt is disabled and the clstat bit is cleared bit 10 trgien: trigger interrupt enable bit 1 = a trigger event generates an interrupt request 0 = trigger event interrupts are disabled and the trgstat bit is cleared bit 9 itb: independent time base mode bit ( 3 ) 1 = phasex/sphasex register provides time base period for this pwm generator 0 = ptper register provides timing for this pwm generator bit 8 mdcs: master duty cycle register select bit ( 3 ) 1 = mdc register provides duty cycle information for this pwm generator 0 = pdcx/sdcx register provides duty cycle information for this pwm generator bit 7-6 dtc<1:0>: dead-time control bits 11 = reserved 10 = dead-time function is disabled 01 = negative dead time is actively applied for all output modes 00 = positive dead time is actively applied for all output modes bit 5-3 unimplemented: read as 0 note 1: software must clear the interrupt status here and the corresponding ifsx bit in the interrupt controller. 2: the independent time base mode (itb = 1 ) must be enabled to use center-aligned mode. if itb = 0 , the cam bit is ignored. 3: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. 4: to operate in external period reset mode, configure fclconx dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 206 ? 2008-2014 microchip technology inc. bit 2 cam: center-aligned mode enable bit ( 2 , 3 ) 1 = center-aligned mode is enabled 0 = center-aligned mode is disabled bit 1 xpres: external pwm reset control bit ( 4 ) 1 = current-limit source resets the time base for this pwm generator if it is in independent time base (itb) mode 0 = external pins do not affect pwm time base bit 0 iue: immediate update enable bit 1 = updates to the active mdc/pdcx/sdcx registers are immediate 0 = updates to the active mdc/pdcx/sdcx regi sters are synchronized to the pwm time base register 15-6: pwmconx: pwmx control register (continued) note 1: software must clear the interrupt status here and the corresponding ifsx bit in the interrupt controller. 2: the independent time base mode (itb = 1 ) must be enabled to use center-aligned mode. if itb = 0 , the cam bit is ignored. 3: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. 4: to operate in external period reset mode, configure fclconx ? 2008-2014 microchip technology inc. ds70000318g-page 207 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-7: pdcx: pwmx generator duty cycle register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 pdcx<15:0>: pwm generator # duty cycle value bits note 1: in independent pwm mode, the pdcx register controls the pwmxh duty cycle only. in complementary, redundant and push-pull pwm modes, the pdcx register controls the duty cycle of both the pwmxh and pwmxl. the smallest pulse width that can be generated on the pwm output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of period-0x0008. 2: as the duty cycle gets closer to 0% or 100% of the pwm period (0 ns-40 ns, depending on the mode of operation), the pwm duty cycle resolution will degrade from 1 lsb to 3 lsbs. register 15-8: sdcx: pwmx secondary duty cycle register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 sdcx<15:0>: secondary duty cycle for pwmxl output pin bits note 1: the sdcx register is used in independent pwm mode only. when used in independent pwm mode, the sdcx register controls the pwmxl duty cycle. the smallest pulse width that can be generated on the pwm output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of period-0x0008. 2: as the duty cycle gets closer to 0% or 100% of the pwm period (0 ns-40 ns, depending on the mode of operation), the pwm duty cycle resolution will degrade from 1 lsb to 3 lsbs. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 208 ? 2008-2014 microchip technology inc. register 15-9: phasex: pwmx primary phase-shift register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasex<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasex<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 phasex<15:0>: pwm phase-shift value or independent time base period for this pwm generator bits note 1: if pwmconx ? 2008-2014 microchip technology inc. ds70000318g-page 209 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-10: sphase x : pwm x secondary phase-shift register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sphasex<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sphasex<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 sphasex<15:0>: secondary phase offset for pwmxl output pin bits (used in independent pwm mode only) note 1: if pwmconx dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 210 ? 2008-2014 microchip technology inc. . register 15-11: dtrx: pwmx dead-time register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 d t r x < 1 3 : 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtrx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-0 dtrx<13:0>: unsigned 14-bit dead-time value for pwmx dead-time unit bits register 15-12: altdtrx: pwmx alternate dead-time register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 altdtrx<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 altdtr <7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-0 altdtrx<13:0>: unsigned 14-bit dead-time value for pwmx dead-time unit bits downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 211 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-13: trgconx: pwmx trigger control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 trgdiv3 trgdiv2 trgdiv1 trgdiv0 bit 15 bit 8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtm ( 1 ) trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 trgdiv<3:0> : trigger # output divider bits 1111 = trigger output for every 16th trigger event 1110 = trigger output for every 15th trigger event 1101 = trigger output for every 14th trigger event 1100 = trigger output for every 13th trigger event 1011 = trigger output for every 12th trigger event 1010 = trigger output for every 11th trigger event 1001 = trigger output for every 10th trigger event 1000 = trigger output for every 9th trigger event 0111 = trigger output for every 8th trigger event 0110 = trigger output for every 7th trigger event 0101 = trigger output for every 6th trigger event 0100 = trigger output for every 5th trigger event 0011 = trigger output for every 4th trigger event 0010 = trigger output for every 3rd trigger event 0001 = trigger output for every 2nd trigger event 0000 = trigger output for every trigger event bit 11-8 unimplemented: read as 0 bit 7 dtm: dual trigger mode bit ( 1 ) 1 = secondary trigger event is combined with the primary trigger event to create the pwm trigger. 0 = secondary trigger event is not combined with the primary trigger event to create the pwm trigger; two separate pwm triggers are generated bit 6 unimplemented: read as 0 bit 5-0 trgstrt<5:0>: trigger postscaler start enable select bits 111111 = wait 63 pwm cycles before generating the first trigger event after the module is enabled 000010 = wait 1 pwm cycles before generating the first trigger event after the module is enabled 000001 = wait 1 pwm cycle before generating the first trigger event after the module is enabled 000000 = wait 0 pwm cycles before generating the first trigger event after the module is enabled note 1: the secondary generator cannot generate pwm trigger interrupts. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 212 ? 2008-2014 microchip technology inc. register 15-14: ioconx: pw mx i/o control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 penh penl polh poll pmod1 ( 1 ) pmod0 ( 1 ) ovrenh ovrenl bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ovrdat1 ovrdat0 fltdat1 ( 2 ) fltdat0 ( 2 ) cldat1 ( 2 ) cldat0 ( 2 ) swap osync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 penh: pwmh output pin ownership bit 1 = pwm module controls the pwmxh pin 0 = gpio module controls the pwmxh pin bit 14 penl: pwml output pin ownership bit 1 = pwm module controls the pwmxl pin 0 = gpio module controls the pwmxl pin bit 13 polh: pwmh output pin polarity bit 1 = pwmxh pin is active-low 0 = pwmxh pin is active-high bit 12 poll: pwml output pin polarity bit 1 = pwmxl pin is active-low 0 = pwmxl pin is active-high bit 11-10 pmod<1:0>: pwm # i/o pin mode bits ( 1 ) 11 = pwm i/o pin pair is in the true independent output mode 10 = pwm i/o pin pair is in the push-pull output mode 01 = pwm i/o pin pair is in the redundant output mode 00 = pwm i/o pin pair is in the complementary output mode bit 9 ovrenh: override enable for pwmxh pin bit 1 = ovrdat<1> provides data for output on the pwmxh pin 0 = pwm generator provides data for the pwmxh pin bit 8 ovrenl: override enable for pwmxl pin bit 1 = ovrdat<0> provides data for output on the pwmxl pin 0 = pwm generator provides data for the pwmxl pin bit 7-6 ovrdat<1:0>: data for pwmxh and pwmxl pins if override is enabled bits if overenh = 1 , then ovrdat<1> provides data for pwmxh if overenl = 1 , then ovrdat<0> provides data for pwmxl bit 5-4 fltdat<1:0>: state for pwmxh and pwmxl pins if fltmod is enabled bits ( 2 ) fclconx ? 2008-2014 microchip technology inc. ds70000318g-page 213 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 3-2 cldat<1:0>: state for pwmxh and pwmxl pins if clmode is enabled bits ( 2 ) fclconx dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 214 ? 2008-2014 microchip technology inc. register 15-15: fclconx: pwmx fau lt current-limit control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifltmod clsrc4 ( 2 , 3 ) clsrc3 ( 2 , 3 ) clsrc2 ( 2 , 3 ) clsrc1 ( 2 , 3 ) clsrc0 ( 2 , 3 ) clpol ( 1 ) clmod bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fltsrc4 ( 2 , 3 ) fltsrc3 ( 2 , 3 ) fltsrc2 ( 2 , 3 ) fltsrc1 ( 2 , 3 ) fltsrc0 ( 2 , 3 ) fltpol ( 1 ) fltmod1 fltmod0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ifltmod: independent fault mode enable bit 1 = independent fault mode: current-limit input maps fltdat1 to pwmxh output and the fault input maps fltdat0 to the pwmxl output. the cldat<1:0> bits are not used for override functions. 0 = normal fault mode: current-limit feature maps cldat<1:0> bits to the pwmxh and pwmxl outputs. the pwm fault feature maps fltdat<1:0> to the pwmxh and pwmxl outputs. bit 14-10 clsrc<4:0>: current-limit control signal source select for pwm # generator bits ( 2 , 3 ) 11111 = reserved 01000 = reserved 00111 = fault 8 00110 = fault 7 00101 = fault 6 00100 = fault 5 00011 = fault 4 00010 = fault 3 00001 = fault 2 00000 = fault 1 bit 9 clpol: current-limit polarity for pwm generator # bit ( 1 ) 1 = the selected current-limit source is active-low 0 = the selected current-limit source is active-high bit 8 clmod: current-limit mode enable bit for pwm generator # bit 1 = current-limit function is enabled 0 = current-limit function is disabled note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. 2: when independent fault mode is enabled (ifltmod = 1 ), and fault 1 is used for current-limit mode (clsrc<4:0> = b0000 ), the fault control source select bits (fltsrc<4:0>) should be set to an unused fault source to prevent fault 1 from disabling both the pwmxl and pwmxh outputs. 3: when independent fault mode is enabled (ifltmod = 1 ) and fault 1 is used for fault mode (fltsrc<4:0> = b0000 ), the current-limit control source select bits (clsrc<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the pwmxh and pwmxl outputs. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 215 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 7-3 fltsrc<4:0>: fault control signal source select for pwm generator # bits ( 2 , 3 ) 11111 = reserved 01000 = reserved 00111 = fault 8 00110 = fault 7 00101 = fault 6 00100 = fault 5 00011 = fault 4 00010 = fault 3 00001 = fault 2 00000 = fault 1 bit 2 fltpol: fault polarity for pwm generator # bit ( 1 ) 1 = the selected fault source is active-low 0 = the selected fault source is active-high bit 1-0 fltmod<1:0>: fault mode for pwm generator # bits 11 = fault input is disabled 10 = reserved 01 = the selected fault source forces the pwmxh and pwmxl pins to fltdat values (cycle) 00 = the selected fault source forces the pwmxh and pwmxl pins to fltdat values (latched condition) register 15-15: fclconx: pwmx fault curre nt-limit control register (continued) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. 2: when independent fault mode is enabled (ifltmod = 1 ), and fault 1 is used for current-limit mode (clsrc<4:0> = b0000 ), the fault control source select bits (fltsrc<4:0>) should be set to an unused fault source to prevent fault 1 from disabling both the pwmxl and pwmxh outputs. 3: when independent fault mode is enabled (ifltmod = 1 ) and fault 1 is used for fault mode (fltsrc<4:0> = b0000 ), the current-limit control source select bits (clsrc<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the pwmxh and pwmxl outputs. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 216 ? 2008-2014 microchip technology inc. register 15-16: trigx: pwmx primary trigger compare value register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgcmp<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 trgcmp<7:3> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 trgcmp<15:3>: trigger control value bits when primary pwm functions in the local time base, this register contains the compare values that can trigger the adc module. bit 2-0 unimplemented: read as 0 register 15-17: strigx: pwmx seco ndary trigger compare value register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 strgcmp<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 strgcmp<7:3> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 strgcmp<15:3>: secondary trigger control value bits when secondary pwm functions in the local time base, this register contains the compare values that can trigger the adc module. bit 2-0 unimplemented: read as 0 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 217 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 15-18: lebconx: leading-e dge blanking co ntrol register ( 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phr phf plr plf fltleben clleben leb6 leb5 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 leb4 leb3 leb2 leb1 leb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 phr: pwmxh rising edge trigger enable bit 1 = rising edge of pwmxh will trigger the leb counter 0 = leb ignores the rising edge of pwmxh bit 14 phf: pwmh falling edge trigger enable bit 1 = falling edge of pwmxh will trigger the leb counter 0 = leb ignores the falling edge of pwmxh bit 13 plr: pwml rising edge trigger enable bit 1 = rising edge of pwmxl will trigger the leb counter 0 = leb ignores the rising edge of pwmxl bit 12 plf: pwml falling edge trigger enable bit 1 = falling edge of pwmxl will trigger the leb counter 0 = leb ignores the falling edge of pwmxl bit 11 fltleben: fault input leb enable bit 1 = leading-edge blanking is applied to selected fault input 0 = leading-edge blanking is not applied to selected fault input bit 10 clleben: current-limit leb enable bit 1 = leading-edge blanking is applied to selected current-limit input 0 = leading-edge blanking is not applied to selected current-limit input bit 9-3 leb<6:0>: leading-edge blanking for current-limit and fault inputs bits the value is 8.32 nsec increments. bit 2-0 unimplemented: read as 0 note 1: configure this register in word format. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 218 ? 2008-2014 microchip technology inc. register 15-19: pwmcapx: primary pwmx time base capture register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pwmcap<15:8> ( 1 , 2 ) bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 u-0 u-0 u-0 pwmcap<7:3> ( 1 , 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 pwmcap<15:3>: captured pwm time base value bits ( 1 , 2 ) the value in this register represents the captured pwm time base value when a leading edge is detected on the current-limit input. bit 2-0 unimplemented: read as 0 note 1: the capture feature is only available on the primary output (pwmxh). 2: this feature is active only after leb processing on the current-limit input signal is complete. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 219 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 16.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices can be serial eeproms, shift registers, display drivers, analog-to-digital converters and so on. the spi module is compatible with spi and siop from motorola ? . the spi module consists of a 16-bit shift register, spixsr (where x = 1), used for shifting data in and out, and a buffer register, spixbuf. a control register, spixcon, configures the module. additionally, a status register, spixstat, indicates status conditions. the serial interface consists of the following four pins: sdix (serial data input) sdox (serial data output) sckx (shift clock input or output) ssx (active-low slave select). in master mode operation, sck is a clock output; in slave mode, it is a clock input. figure 16-1: spix mo dule block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to serial peripheral interface (spi) (ds70206) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. internal data bus sdix sdox ssx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler sync spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock clock control secondary prescaler 1:1 to 1:8 spixrxb spixtxb downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 220 ? 2008-2014 microchip technology inc. register 16-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 spien spisidl bit 15 bit 8 u-0 r/c-0 u-0 u-0 u-0 u-0 r-0 r-0 spirov spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 spien: spix enable bit 1 = enables module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables module bit 14 unimplemented: read as 0 bit 13 spisidl: spix stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 spirov: spix receive overflow flag bit 1 = a new byte/word is completely received and discarded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred bit 5-2 unimplemented: read as 0 bit 1 spitbf: spix transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty. automatically set in hardware when cpu writes the spixbuf location, loading spixtxb. automatically cleared in hardware when the spix module transfers data from spixtxb to spixsr. bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is not complete, spixrxb is empty. automatically set in hardware w hen spix transfers data from spixsr to spixrxb. automatically cleared in hardware when core reads the spixbuf location, reading spixrxb. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 221 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 16-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dissck dissdo mode16 smp cke ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ( 3 ) ckp msten spre2 ( 2 ) spre1 ( 2 ) spre0 ( 2 ) ppre1 ( 2 ) ppre0 ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 dissck: disable sckx pin bit (spi master modes only) 1 = internal spi clock is disabled; pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit ( 1 ) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable bit (slave mode) ( 3 ) 1 = ssx pin is used for slave mode 0 = ssx pin is not used by module; pin controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in the framed spi modes. program this bit to 0 for the framed spi modes (frmen = 1 ). 2: do not set both primary and secondary prescalers to a value of 1:1. 3: this bit must be cleared when frmen = 1 . downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 222 ? 2008-2014 microchip technology inc. bit 4-2 spre<2:0>: secondary prescale bits (master mode) ( 2 ) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) ( 2 ) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 16-2: spi x con1: spix control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. program this bit to 0 for the framed spi modes (frmen = 1 ). 2: do not set both primary and secondary prescalers to a value of 1:1. 3: this bit must be cleared when frmen = 1 . downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 223 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 16-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 frmdly bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 frmen : framed spix support bit 1 = framed spix support is enabled (ssx pin used as frame sync pulse input/output) 0 = framed spix support is disabled bit 14 spifsd : spix frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol : frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as 0 bit 1 frmdly : frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 unimplemented: this bit must not be set to 1 by the user application downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 224 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 225 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 17.0 inter-integrated circuit (i 2 c?) the inter-integrated circuit (i 2 c) module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard with a 16-bit interface. the i 2 c module has a 2-pin interface, where: the sclx pin is clock the sdax pin is data the i 2 c module offers the following key features: i 2 c interface supporting both master and slave modes of operation i 2 c slave mode supports 7-bit and 10-bit addressing i 2 c master mode supports 7-bit and 10-bit addressing i 2 c port allows bidirectional transfers between master and slaves serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly 17.1 operating modes the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7-bit and 10-bit addressing. the i 2 c module can operate either as a slave or a master on an i 2 c bus. the following types of i 2 c operation are supported: i 2 c slave operation with 7-bit addressing i 2 c slave operation with 10-bit addressing i 2 c master operation with 7-bit or 10-bit addressing note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to inter-integrated circuit (i 2 c?) (ds70000195) in the ?dspic33/pic24 family reference man- ual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 226 ? 2008-2014 microchip technology inc. figure 17-1: i2cx block diagram ( x = 1) internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 227 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 17.2 i 2 c registers i2cxcon and i2cxstat are control and status registers. the i2cxcon register is readable and writable. the lower six bits of i2cxstat are read-only. the remaining bits of the i2cxstat are read/write: i2cxrsr is the shift register used for shifting data internal to the module and the user application has no access to it i2cxrcv is the receive buffer and the register to which data bytes are written, or from which data bytes are read i2cxtrn is the transmit register to which bytes are written during a transmit operation the i2cxadd register holds the slave address a status bit, add10, indicates 10-bit addressing mode the i2cxbrg acts as the baud rate generator (brg) reload value in receive operations, i2cxrsr and i2cxrcv together form a double-buffered receiver. when i2cxrsr receives a complete byte, it is transferred to i2cxrcv, and an interrupt pulse is generated. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 228 ? 2008-2014 microchip technology inc. register 17-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hc = hardware clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module, and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module; all i 2 c? pins are controlled by port functions. bit 14 unimplemented: read as 0 bit 13 i2csidl: i2cx stop in idle mode bit 1 = discontinues module operation when device enters an idle mode 0 = continues module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = releases sclx clock 0 = holds sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write 0 to initiate stretch and write 1 to release clock). hardware clear at beginning of slave transmission. hardware clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write 1 to release clock). hardware clear at beginning of slave transmission. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi mode is enabled; all addresses are acknowledged 0 = ipmi mode is disabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control is disabled 0 = slew rate control is enabled bit 8 smen: smbus input levels bit 1 = enables i/o pin thresholds compliant with smbus specification 0 = disables smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enables interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address is disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with the sclrel bit. 1 = enables software or receive clock stretching 0 = disables software or receive clock stretching downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 229 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the software initiates an acknowledge sequence. 1 = sends nack during acknowledge 0 = sends ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiates acknowledge sequence on sdax and sclx pins and transmits the ackdt data bit. hardware is clear at end of master acknowledge sequence. 0 = acknowledge sequence is not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware is clear at end of eighth bit of master receive data byte. 0 = receive sequence is not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiates stop condition on sdax and sclx pins. hardware is clear at end of master stop sequence. 0 = stop condition is not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiates repeated start condition on sdax and sclx pins. hardware is clear at end of master repeated start sequence. 0 = repeated start condition is not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiates start condition on sdax and sclx pins. hardware is clear at end of master start sequence. 0 = start condition is not in progress register 17-1: i2cxcon: i2cx control register (continued) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 230 ? 2008-2014 microchip technology inc. register 17-2: i2cxstat: i2cx status register r-0, hsc r-0, hsc u-0 u-0 u-0 r/c-0, hsc r-0, hsc r-0, hsc ackstat trstat bcl gcstat add10 bit 15 bit 8 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0 , hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: c = clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown hs = hardware settable bit bit 15 ackstat: acknowledge status bit (when operating as i 2 c? master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware is set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware is set at beginning of master transmission. hardware is clear at end of slave acknowledge. bit 13-11 unimplemented: read as 0 bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware is set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware is set when address matches general call address. hardware is clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware is set at match of 2nd byte of matched 10-bit address. hardware is clear at stop detection. bit 7 iwcol: i2cx write collision detect bit 1 = an attempt to write to the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware is set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: i2cx receive overflow flag bit 1 = a byte was received while the i2cxrcv register is still holding the previous byte 0 = no overflow hardware is set at attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was a device address hardware is clear at device address match. hardware is set by reception of slave byte. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 231 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware is set or clear when start, repeated start or stop is detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware is set or clear when start, repeated start or stop is detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read C indicates data transfer is output from slave 0 = write C indicates data transfer is input to slave hardware is set or clear after reception of an i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive is complete, i2cxrcv is full 0 = receive is not complete, i2cxrcv is empty hardware is set when i2cxrcv is written with a received byte. hardware is clear when soft ware reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit is in progress, i2cxtrn is full 0 = transmit is complete, i2cxtrn is empty hardware is set when software writes to i2cxtrn. hardware is clear at completion of data transmission. register 17-2: i2cxstat: i2cx status register (continued) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 232 ? 2008-2014 microchip technology inc. register 17-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 amsk<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9-0 amsk<9:0>: mask for address bit x select bits 1 = enables masking for bit x of incoming message address; bit match is not required in this position 0 = disables masking for bit x; bit match is required in this position downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 233 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 18.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 device families. the uart is a full-duplex, asynchronous system that can commu- nicate with peripheral devices, such as personal computers, lin/j2602, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins and also includes an irda ? encoder and decoder. the primary features of the uart module are: full-duplex, 8-bit or 9-bit data transmission through the uxtx and uxrx pins even, odd or no parity options (for 8-bit data) one or two stop bits hardware flow control option with uxcts and uxrts pins fully integrated baud rate generator with 16-bit prescaler baud rates ranging from 12.5 mbps to 38 bps at 50 mips 4-deep first-in first-out (fifo) transmit data buffer 4-deep fifo receive data buffer parity, framing and buffer overrun error detection support for 9-bit mode with address detect (9th bit = 1 ) transmit and receive interrupts a separate interrupt for all uart error conditions loopback mode for diagnostic support support for sync and break characters support for automatic baud rate detection irda encoder and decoder logic 16x baud clock output for irda ? support a simplified block diagram of the uart module is shown in figure 1 . the uart module consists of these key hardware elements: baud rate generator asynchronous transmitter asynchronous receiver figure 1: uart1 simplified block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to uart (ds70188) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. u1rx hardware flow control uart receiver uart transmitter u1tx baud rate generator u 1r ts /bclk1 irda ? u 1c ts downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 234 ? 2008-2014 microchip technology inc. register 18-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten ( 1 ) usidl iren ( 2 ) rtsmd u e n 1u e n 0 bit 15 bit 8 r/w-0, hc r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit ( 1 ) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches, uartx power cons umption is minimal bit 14 unimplemented: read as 0 bit 13 usidl: uartx stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit ( 2 ) 1 = irda encoder and decoder are enabled 0 = irda encoder and decoder are disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as 0 bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and bclk pins are enabled and used; uxcts pin is controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclk pins are controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt is generated on falling edge, bit is cleared in hardware on the following rising edge 0 = no wake-up is enabled bit 6 lpback: uartx loopback mode select bit 1 = enables loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character C requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement is disabled or has completed note 1: refer to uart (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 235 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 4 urxinv: uartx receive polarity inversion bit 1 = uxrx idle state is 0 0 = uxrx idle state is 1 bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 18-1: uxmode: uart x mode register (continued) note 1: refer to uart (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 236 ? 2008-2014 microchip technology inc. register 18-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r/w-0 r-0 r-1 utxisel1 utxinv utxisel0 utxbrk utxen ( 1 ) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel1 urxisel0 adden ridle perr ferr oerr urxda bit 7 bit 0 legend: hc = hardware clearable bit c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: uartx transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register (tsr), and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: uartx transmit polarity inversion bit if iren = 0 : 1 = uxtx idle state is 0 0 = uxtx idle state is 1 if iren = 1 : 1 =irda ? encoded uxtx idle state is 1 0 = irda encoded uxtx idle state is 0 bit 12 unimplemented: read as 0 bit 11 utxbrk: uartx transmit break bit 1 = sends sync break on next transmission C start bit, followed by twelve 0 bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission is disabled or has completed bit 10 utxen: uartx transmit enable bit ( 1 ) 1 = transmit is enabled, uxtx pin is controlled by uartx 0 = transmit is disabled, any pending transmission is aborted and buffer is reset; uxtx pin is controlled by port bit 9 utxbf: uartx transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full; at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: uartx receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer, making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the uxrsr to the receive buffer; receive buffer has one or more characters note 1: refer to uart (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for transmit operation. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 237 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enable; if 9-bit mode is not selected, this does not take effect 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (clear/read-only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed; clearing a previously set oerr bit ( 1 ? 0 transition) will reset the receiver buffer and the uxrsr to the empty state bit 0 urxda: uartx receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 18-2: u x sta: uart x status and control register (continued) note 1: refer to uart (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for transmit operation. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 238 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 239 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 19.0 high-speed 10-bit analog-to-digital converter (adc) dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices provide high-speed, successive approximation analog-to-digital conversions to support applications, such as ac/dc and dc/dc power converters. 19.1 features overview the adc module comprises the following features: 10-bit resolution unipolar inputs up to two successive approximation registers (sars) up to 12 external input channels up to two internal analog inputs dedicated result register for each analog input 1 lsb accuracy at 3.3v single supply operation 4 msps conversion rate at 3.3v (devices with two sars) 2 msps conversion rate at 3.3v (devices with one sar) low-power cmos technology 19.2 module description this adc module is designed for applications that require low latency between the request for conversion and the resultant output data. typical applications include: ac/dc power supplies dc/dc converters power factor correction (pfc) this adc works with the high-speed pwm module in power control applications that require high-frequency control loops. this module can sample and convert two analog inputs in a 0.5 microsecond when two sars are used. this small conversion delay reduces the phase lag between measurement and control system response. up to five inputs may be sampled at a time (four inputs from the dedicated sample-and-hold circuits and one from the shared sample-and-hold circuit). if multiple inputs request conversion, the adc will convert them in a sequential manner, starting with the lowest order input. this adc design provides each pair of analog inputs (an1, an0), (an3, an2),..., the ability to specify its own trigger source out of a maximum of sixteen different trigger sources. this capability allows this adc to sample and convert analog inputs that are associated with pwm generators operating on independent time bases (itbs). the user application typically requires synchronization between analog data sampling and pwm output to the application circuit. the very high-speed operation of this adc module allows data on demand. in addition, several hardware features have been added to the peripheral interface to improve real-time performance in a typical dsp-based application. result alignment options automated sampling external conversion start control two internal inputs to monitor the intref internal reference and the extref input signal 19.3 module functionality the high-speed, 10-bit adc module is designed to support power conversion applications when used with the high-speed pwm module. the adc may have one or two sar modules, depending on the device variant. if two sars are present on a device, two conversions can be processed at a time, yielding 4 msps conversion rate. if only one sar is present on a device, only one conversion can be processed at a time, yielding 2 msps conversion rate. the high-speed 10-bit adc produces two 10-bit conversion results in a 0.5 microsecond. the adc module supports up to 12 external analog inputs and two internal analog inputs. to monitor reference voltage, two internal inputs, an12 and an13, are connected to the extref and intref voltages, respectively. the analog reference voltage is defined as the device supply voltage (av dd /av ss ). block diagrams of the adc module are shown in figure 19-1 through figure 19-6 . note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to high-speed 10-bit analog-to-digital converter (adc) (ds70000321) in the ?dspic33/pic24 family reference man- ual? , which is available on the microchip web site ( www.microchip.com) . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 240 ? 2008-2014 microchip technology inc. figure 19-1: adc block diagram for dspic33fj06gs101 devices with one sar even numbered inputs with dedicated shared sample-and-hold data format sar core six registers 16-bit sample-and-hold (s&h) circuits bus interface an0 an1 an3 an6 an7 an2 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 241 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 19-2: adc block diagram for dspic33fj06gs102 devices with one sar even numbered inputs with dedicated shared sample-and-hold data format sar core six registers 16-bit sample-and-hold (s&h) circuits bus interface an0 an2 an1 an4 an5 an3 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 242 ? 2008-2014 microchip technology inc. figure 19-3: adc block diagram for dspic33fj06gs202 devices with one sar an12 (1) an13 (2) even numbered inputs with dedicated shared sample-and-hold data format sar core eight registers 16-bit sample-and-hold (s&h) circuits bus interface an0 an2 an1 an4 an5 an3 (intref) (extref) note 1: an12 (extref) is an internal analog input. to measure the voltage at an12 (extref), a n analog comparator must be enabled and extref must be selected as the comparator reference. 2: an13 (intref) is an internal analog input and is not available on a pin. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 243 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 19-4: adc block diagram for dspic33fj16gs402/404 devices with one sar even numbered inputs with dedicated shared sample-and-hold data format sar core eight registers 16-bit sample-and-hold (s&h) circuits bus interface an0 an2 an1 an5 an6 an7 an3 an4 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 244 ? 2008-2014 microchip technology inc. figure 19-5: adc block diagram for dspic33fj16gs502 devices with two sars an12 (1) an13 (2) even numbered inputs with dedicated odd numbered inputs with shared s&h even numbered inputs with shared s&h data format sar core five registers 16-bit sar core sample-and-hold (s&h) circuits bus interface an0 an2 an6 an1 an3 data format five registers 16-bit an4 an5 an7 (intref) (extref) note 1: an12 (extref) is an internal analog input. to measure the voltage at an12 (extref), a n analog comparator must be enabled and extref must be selected as the comparator reference. 2: an13 (intref) is an internal analog input and is not available on a pin. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 245 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 19-6: adc block diagram for dspic33fj16gs504 devices with two sars an12 (1) an13 (2) even numbered inputs with dedicated odd numbered inputs with shared s&h even numbered inputs with shared s&h data format sar core seven registers 16-bit sar core sample-and-hold (s&h) circuits bus interface an0 an2 an6 an1 an3 an8 an10 data format seven registers 16-bit an4 an5 an7 an9 an11 (intref) (extref) note 1: an12 (extref) is an internal analog input. to measure the voltage at an12 (extref), an anal og comparator must be enabled and extref must be selected as the comparator reference. 2: an13 (intref) is an internal analog input and is not available on a pin. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 246 ? 2008-2014 microchip technology inc. 19.4 adc control registers the adc module uses the following control and status registers: adcon: analog-to-digital control register adstat: analog-to-digital status register adbase: analog-to-digital base register(1,2) adpcfg: analog-to-digital port configuration register adcpc0: analog-to-digital convert pair control register 0 adcpc1: analog-to-digital convert pair control register 1 adcpc2: analog-to-digital convert pair control register 2(1) adcpc3: analog-to-digital convert pair control register 3(1) the adcon register controls the operation of the adc module. the adstat register displays the status of the conversion processes. the adpcfg registers configure the port pins as analog inputs or as digital i/o. the adcpcx registers control the triggering of the adc conversions. see register 19-1 through register 19-8 for detailed bit configurations. note: a unique feature of the adc module is its ability to sample inputs in an asynchronous manner. individual sample-and-hold circuits can be triggered independently of each other. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 247 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 19-1: adcon: analog-to -digital control register r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 adon adsidl slowclk ( 1 ) g s w t r g f o r m ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-1 r/w-1 eie ( 1 ) order ( 1 , 2 ) seqsamp ( 1 , 2 ) asyncsamp ( 1 ) adcs2 ( 1 ) adcs1 ( 1 ) adcs0 ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 adon: analog-to-digital operating mode bit 1 = analog-to-digital converter (adc) module is operating 0 = adc converter is off bit 14 unimplemented: read as 0 bit 13 adsidl: adc stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12 slowclk: enable the slow clock divider bit ( 1 ) 1 = adc is clocked by the auxiliary pll (aclk) 0 = adc is clock by the primary pll (f vco ) bit 11 unimplemented: read as 0 bit 10 gswtrg: global software trigger bit when this bit is set by the user, it will trigger conversions if selected by the trgsrc<4:0> bits in th e adcpcx registers. this bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). bit 9 unimplemented: read as 0 bit 8 form: data output format bit ( 1 ) 1 = fractional (d out = dddd dddd dd00 0000 ) 0 = integer (d out = 0000 00dd dddd dddd ) bit 7 eie: early interrupt enable bit ( 1 ) 1 = interrupt is generated after first conversion is completed 0 = interrupt is generated after second conversion is completed bit 6 order: conversion order bit ( 1 , 2 ) 1 = odd numbered analog input is converted first, followed by conversion of even numbered input 0 = even numbered analog input is converted first, followed by conversion of odd numbered input bit 5 seqsamp: sequential sample enable bit ( 1 , 2 ) 1 = shared sample-and-hold (s&h) circuit is sampled at the start of the second conversion if order = 0 . if order = 1 , then the shared s&h is sampled at the start of the first conversion. 0 = shared s&h is sampled at the same time the dedicated s&h is sampled if the shared s&h is not currently busy with an existing conversion process. if the shared s&h is busy at the time the dedicated s&h is sampled, then the shared s&h will sample at the start of the new conversion cycle. note 1: these control bits can only be changed while adc is disabled (adon = 0 ). 2: these bits are only available on devices with one sar. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 248 ? 2008-2014 microchip technology inc. bit 4 asyncsamp: asynchronous dedicated s&h sampling enable bit ( 1 ) 1 = the dedicated s&h is constantly sampling and then terminates sampling as soon as the trigger pulse is detected 0 = the dedicated s&h starts sampling when the trigger event is detected and completes the sampling process in two adc clock cycles bit 3 unimplemented: read as 0 bit 2-0 adcs<2:0>: analog-to-digital conversion clock divider select bits ( 1 ) 111 = fadc/8 110 = fadc/7 101 = fadc/6 100 = fadc/5 011 = fadc/4 (default) 010 = fadc/3 001 = fadc/2 000 = fadc/1 register 19-1: adcon: anal og-to-digital control register (continued) note 1: these control bits can only be changed while adc is disabled (adon = 0 ). 2: these bits are only available on devices with one sar. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 249 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 19-2: adstat: analog-to-digital status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/c-0, hs r/c-0, hs r/c-0, hs r/c- 0, hs r/c-0, hs r/c-0, hs r/c-0, hs p6rdy p5rdy p4rdy p3rdy p2rdy p1rdy p0rdy bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6 p6rdy: conversion data for pair 6 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. bit 5 p5rdy: conversion data for pair 5 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. bit 4 p4rdy: conversion data for pair 4 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. bit 3 p3rdy: conversion data for pair 3 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. bit 2 p2rdy: conversion data for pair 2 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. bit 1 p1rdy: conversion data for pair 1 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. bit 0 p0rdy: conversion data for pair 0 ready bit bit is set when data is ready in buffer, cleared when a 0 is written to this bit. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 250 ? 2008-2014 microchip technology inc. register 19-3: adbase: analog-to-digital base register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adbase<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 adbase<7:1> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-1 adbase<15:1>: analog-to-digital base bits this register contains the base address of the users adc interrupt service routine jump table. this register, when read, contains the sum of the adbase register contents and the encoded value of the pxrdy status bits. the encoder logic provides the bit number of the highest priority pxrdy bits, where p0rdy is the highest priority and p6rdy is the lowest priority. bit 0 unimplemented: read as 0 note 1: the encoding results are shifted left two bits, so bits 1-0 of the result are always zero. 2: as an alternative to using the adbase register, the adcp0-6 adc pair conversion complete interrupts can be used to invoke a to d conversion completion routines for individual adc input pairs. register 19-4: adpcfg: analog-to-di gital port configuration register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 p c f g < 1 1 : 8 > ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg<7:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-0 pcfg<11:0>: analog-to-digital port configuration control bits ( 1 ) 1 = port pin in digital mode; port read input is enabled, analog-to-digital input multiple xer is connected to av ss 0 = port pin in analog mode; port read input is disabled, analog-to-digital samples the pin voltage note 1: not all pcfgx bits are available on all devices. see figure 19-1 through figure 19-6 for the available analog pins (pcfgx = anx, where x = 0-11). downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 251 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 19-5: adcpc0: analog-to-digital convert pair control register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen1 pend1 swtrg1 trgsrc14 trgsrc13 trgsrc12 trgsrc11 trgsrc10 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen0 pend0 swtrg0 trgsrc04 trgsrc03 trgsrc02 trgsrc01 trgsrc00 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 irqen1: interrupt request enable 1 bit 1 = enables irq generation when requested conversion of channels an3 and an2 is completed 0 = irq is not generated bit 14 pend1: pending conversion status 1 bit 1 = conversion of channels an3 and an2 is pending; set when selected trigger is asserted 0 = conversion is complete bit 13 swtrg1: software trigger 1 bit 1 = starts conversion of an3 and an2 (if selected by the trgsrcx bits) ( 1 ) this bit is automatically cleared by hardware when the pend1 bit is set. 0 = conversion has not started note 1: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 252 ? 2008-2014 microchip technology inc. bit 12-8 trgsrc1<4:0>: trigger 1 source selection bits selects trigger source for conversion of analog channels an3 and an2. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled bit 7 irqen0: interrupt request enable 0 bit 1 = enables irq generation when requested conversion of channels an1 and an0 is completed 0 = irq is not generated bit 6 pend0: pending conversion status 0 bit 1 = conversion of channels an1 and an0 is pending; set when selected trigger is asserted 0 = conversion is complete bit 5 swtrg0: software trigger 0 bit 1 = starts conversion of an1 and an0 (if selected by the trgsrcx bits) ( 1 ) this bit is automatically cleared by hardware when the pend0 bit is set. 0 = conversion has not started register 19-5: adcpc0: analog-to-digital convert pair control register 0 (continued) note 1: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 253 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 4-0 trgsrc0<4:0>: trigger 0 source selection bits selects trigger source for conversion of analog channels an1 and an0. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled register 19-5: adcpc0: analog-to-digital convert pair control register 0 (continued) note 1: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 254 ? 2008-2014 microchip technology inc. register 19-6: adcpc1: analog-to-digital convert pair control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen3 ( 1 ) pend3 ( 1 ) swtrg3 ( 1 ) trgsrc34 ( 1 ) trgsrc33 ( 1 ) trgsrc32 ( 1 ) trgsrc31 ( 1 ) trgsrc30 ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen2 ( 2 ) pend2 ( 2 ) swtrg2 ( 2 ) trgsrc24 ( 2 ) trgsrc23 ( 2 ) trgsrc22 ( 2 ) trgsrc21 ( 2 ) trgsrc20 ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 irqen3: interrupt request enable 3 bit ( 1 ) 1 = enables irq generation when requested conversion of channels an7 and an6 is completed 0 = irq is not generated bit 14 pend3: pending conversion status 3 bit ( 1 ) 1 = conversion of channels an7 and an6 is pending; set when selected trigger is asserted 0 = conversion is complete bit 13 swtrg3: software trigger 3 bit ( 1 ) 1 = starts conversion of an7 and an6 (if selected by the trgsrcx bits) ( 3 ) this bit is automatically cleared by hardware when the pend3 bit is set. 0 = conversion has not started note 1: these bits are available in the dspic33fj16gs402/404, dspic33fj16gs504, dspic33fj16gs502 and dspic33fj06gs101 devices only. 2: these bits are available in the dspic33fj16gs502, dspic33fj16gs504, dspic33fj06gs102, dspic33fj06gs202 and dspic33fj16gs402/404 devices only. 3: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be performed when the conversion resources are available. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 255 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 12-8 trgsrc3<4:0>: trigger 3 source selection bits ( 1 ) selects trigger source for conversion of analog channels an7 and an6. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled bit 7 irqen2: interrupt request enable 2 bit (( 2 )) 1 = enables irq generation when requested conversion of channels an5 and an4 is completed 0 = irq is not generated bit 6 pend2: pending conversion status 2 bit (( 2 )) 1 = conversion of channels an5 and an4 is pending; set when selected trigger is asserted 0 = conversion is complete bit 5 swtrg2: software trigger 2 bit (( 2 )) 1 = starts conversion of an5 and an4 (if selected by the trgsrcx bits) ( 3 ) this bit is automatically cleared by hardware when the pend2 bit is set. 0 = conversion has not started register 19-6: adcpc1: analog-to-digital convert pair control register 1 (continued) note 1: these bits are available in the dspic33fj16gs402/404, dspic33fj16gs504, dspic33fj16gs502 and dspic33fj06gs101 devices only. 2: these bits are available in the dspic33fj16gs502, dspic33fj16gs504, dspic33fj06gs102, dspic33fj06gs202 and dspic33fj16gs402/404 devices only. 3: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 256 ? 2008-2014 microchip technology inc. bit 4-0 trgsrc2<4:0>: trigger 2 source selection bits ( 2 ) selects trigger source for conversion of analog channels an5 and an4. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled register 19-6: adcpc1: analog-to-digital convert pair control register 1 (continued) note 1: these bits are available in the dspic33fj16gs402/404, dspic33fj16gs504, dspic33fj16gs502 and dspic33fj06gs101 devices only. 2: these bits are available in the dspic33fj16gs502, dspic33fj16gs504, dspic33fj06gs102, dspic33fj06gs202 and dspic33fj16gs402/404 devices only. 3: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be performed when the conversion resources are available. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 257 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 19-7: adcpc2: analog-to-digital convert pair control register 2 ( 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen5 pend5 swtrg5 trgsrc54 trgsrc53 trgsrc52 trgsrc51 trgsrc50 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen4 pend4 swtrg4 trgsrc44 trgsrc43 trgsrc42 trgsrc41 trgsrc40 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 irqen5: interrupt request enable 5 bit 1 = enables irq generation when requested conversion of channels an11 and an10 is completed 0 = irq is not generated bit 14 pend5: pending conversion status 5 bit 1 = conversion of channels an11 and an10 is pending; set when selected trigger is asserted 0 = conversion is complete bit 13 swtrg5: software trigger 5 bit 1 = starts conversion of an11 and an10 (if selected by the trgsrcx bits) ( 2 ) this bit is automatically cleared by hardware when the pend5 bit is set. 0 = conversion has not started note 1: this register is only implemented in the dspic33fj16gs504 devices. 2: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 258 ? 2008-2014 microchip technology inc. bit 12-8 trgsrc5<4:0>: trigger 5 source selection bits selects trigger source for conversion of analog channels an11 and an10. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled bit 7 irqen4: interrupt request enable 4 bit 1 = enables irq generation when requested conversion of channels an9 and an8 is completed 0 = irq is not generated bit 6 pend4: pending conversion status 4 bit 1 = conversion of channels an9 and an8 is pending; set when selected trigger is asserted 0 = conversion is complete bit 5 swtrg4: software trigger 4 bit 1 = starts conversion of an9 and an8 (if selected by the trgsrcx bits) ( 2 ) this bit is automatically cleared by hardware when the pend4 bit is set. 0 = conversion has not started register 19-7: adcpc2: analog-to-digital convert pair control register 2 ( 1 ) (continued) note 1: this register is only implemented in the dspic33fj16gs504 devices. 2: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 259 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 4-0 trgsrc4<4:0>: trigger 4 source selection bits selects trigger source for conversion of analog channels an9 and an8. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled register 19-7: adcpc2: analog-to-digital convert pair control register 2 ( 1 ) (continued) note 1: this register is only implemented in the dspic33fj16gs504 devices. 2: the trigger source must be set as a global software trigger prior to setting this bit to 1 . if other conversions are in progress, then the conversion will be perf ormed when the conversion resources are available. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 260 ? 2008-2014 microchip technology inc. register 19-8: adcpc3: analog-to-digital convert pair control register 3 ( 1 ) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqen6 pend6 swtrg6 trgsrc6<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7 irqen6: interrupt request enable 6 bit 1 = enables irq generation when requested conversion of channels an13 and an12 is completed 0 = irq is not generated bit 6 pend6: pending conversion status 6 bit 1 = conversion of channels an13 and an 12 is pending; set when selected trigger is asserted 0 = conversion is complete bit 5 swtrg6: software trigger 6 bit 1 = starts conversion of an13 (intref) and an12 (extref) (if selected by the trgsrcx bits) ( 2 ) this bit is automatically cleared by hardware when the pend6 bit is set. 0 = conversion has not started note 1: this register is only implemented on the dspic33fj16gs502 and dspic33fj16gs504 devices. 2: the trigger source must be set as global software trigger prior to setting this bit to 1 . if other conversions are in progress, conversion will be performed when the conversion resources are a vailable. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 261 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 bit 4-0 trgsrc6<4:0>: trigger 6 source selection bits selects trigger source for conversion of analog channels an13 and an12. 11111 = timer2 period match 11011 = reserved 11010 = pwm generator 4 current-limit adc trigger 11001 = pwm generator 3 current-limit adc trigger 11000 = pwm generator 2 current-limit adc trigger 10111 = pwm generator 1 current-limit adc trigger 10110 = reserved 10010 = reserved 10001 = pwm generator 4 secondary trigger is selected 10000 = pwm generator 3 secondary trigger is selected 01111 = pwm generator 2 secondary trigger is selected 01110 = pwm generator 1 secondary trigger is selected 01101 = reserved 01100 = timer1 period match 01000 = reserved 00111 = pwm generator 4 primary trigger is selected 00110 = pwm generator 3 primary trigger is selected 00101 = pwm generator 2 primary trigger is selected 00100 = pwm generator 1 primary trigger is selected 00011 = pwm special event trigger is selected 00010 = global software trigger is selected 00001 = individual software trigger is selected 00000 = no conversion is enabled register 19-8: adcpc3: analog-to-digital convert pair control register 3 ( 1 ) note 1: this register is only implemented on the dspic33fj16gs502 and dspic33fj16gs504 devices. 2: the trigger source must be set as global software trigger prior to setting this bit to 1 . if other conversions are in progress, conversion will be performed when the conversion resources are a vailable. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 262 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 263 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 20.0 high-speed analog comparator the dspic33f smps comparator module monitors current and/or voltage transients that may be too fast for the cpu and adc to capture. 20.1 features overview the smps comparator module contains the following major features: 16 selectable comparator inputs up to four analog comparators 10-bit dac for each analog comparator programmable output polarity interrupt generation capability dacout pin to provide dac output dac has three ranges of operation: -av dd /2 - internal reference (intref) - external reference (extref) adc sample and convert trigger capability disable capability reduces power consumption functional support for pwm module: - pwm duty cycle control - pwm period control - pwm fault detect 20.2 module description figure 20-1 shows a functional block diagram of one analog comparator from the smps comparator module. the analog comparator provides high-speed operation with a typical delay of 20 ns. the comparator has a typical offset voltage of 5 mv. the negative input of the comparator is always connected to the dac circuit. the positive input of the comparator is connected to an analog multiplexer that selects the desired source pin. the analog comparator input pins are typically shared with pins used by the analog-to-digital converter (adc) module. both the comparator and the adc can use the same pins at the same time. this capability enables a user to measure an input voltage with the adc and detect voltage transients with the comparator. figure 20-1: high-speed analog co mparator module block diagram note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to high-speed analog comparator (ds70296) in the ?dspic33f/pic24h family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. cmpxa (1) cmpxc (1) dac cmppol 01 av dd /2 intref (2) m u x m u x cmref cmpx (1) insel<1:0> 10 acmpx (trigger to pwm) (1) interrupt request cmpxb (1) cmpxd (1) extref (2) status av ss range dacout dacoe note 1: x = 1, 2, 3 and 4. 2: for the intref and extref values, refer to the dac module specifications ( table 24-43 ) in section 24.0 electrical characteristics . glitch filter pulse generator downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 264 ? 2008-2014 microchip technology inc. 20.3 module applications this module provides a means for the smps dspic ? dsc devices to monitor voltage and currents in a power conversion application. the ability to detect transient conditions and stimulate the dspic dsc processor and/or peripherals, without requiring the processor and adc to constantly monitor voltages or currents, frees the dspic dsc to perform other tasks. the comparator module has a high-speed comparator and an associated 10-bit dac that provides a programmable reference voltage to the inverting input of the comparator. the polarity of the comparator out- put is user-programmable. the output of the module can be used in the following modes: generate an interrupt trigger an adc sample and convert process truncate the pwm signal (current limit) truncate the pwm period (current minimum) disable the pwm outputs (fault latch) the output of the comparator module may be used in multiple modes at the same time, such as: 1) generate an interrupt, 2) have the adc take a sample and con- vert it, and 3) truncate the pwm output in response to a voltage being detected beyond its expected value. the comparator module can also be used to wake-up the system from sleep or idle mode when the analog input voltage exceeds the programmed threshold voltage. 20.4 dac the range of the dac is controlled through an analog multiplexer that selects either av dd /2, an internal ref- erence source, intref, or an external reference source, extref. the full range of the dac (av dd /2) will typically be used when the chosen input source pin is shared with the adc. the reduced range option (intref) will likely be used when monitoring current levels using a current sense resistor. usually, the measured voltages in such applications are small (<1.25v); therefore the option of using a reduced ref- erence range for the comparator extends the available dac resolution in these applications. the use of an external reference enables the user to connect to a reference that better suits their application. dacout, shown in figure 20-1 , can only be associated with a single comparator at a given time. 20.5 interaction with i/o buffers if the comparator module is enabled and a pin has been selected as the source for the comparator, then the chosen i/o pad must disable the digital input buffer associated with the pad to prevent excessive currents in the digital buffer due to analog input voltages. 20.6 digital logic the cmpconx register (see register 20-1 ) provides the control logic that configures the comparator module. the digital logic provides a glitch filter for the comparator output to mask transient signals in less than two instruction cycles. in sleep or idle mode, the glitch filter is bypassed to enable an asynchronous path from the comparator to the interrupt controller. this asynchronous path can be used to wake-up the processor from sleep or idle mode. the comparator can be disabled while in idle mode if the cmpsidl bit is set. if a device has multiple comparators, if any cmpsidl bit is set, then the entire group of comparators will be disabled while in idle mode. this behavior reduces complexity in the design of the clock control logic for this module. the digital logic also provides a one t cy width pulse generator for triggering the adc and generating interrupt requests. the cmpdacx (see register 20-2 ) register provides the digital input value to the reference dac. if the module is disabled, the dac and comparator are disabled to reduce power consumption. 20.7 comparator input range the comparator has a limitation for the input common-mode range (cmr) of (av dd C 1.5v), typical. this means that both inputs should not exceed this range. as long as one of the inputs is within the common-mode range, the comparator output will be correct. however, any input exceeding the cmr limitation will cause the comparator input to be saturated. if both inputs exceed the cmr, the comparator output will be indeterminate. 20.8 dac output range the dac has a limitation for the maximum reference voltage input of (av dd C 1.6) volts. an external reference voltage input should not exceed this value or the reference dac output will become indeterminate. 20.9 comparator registers the comparator module is controlled by the following registers: cmpconx: comparator control x register cmpdacx: comparator dac x control register note: it should be ensured in software that multiple dacoe bits are not set. the output on the dacout pin will be indeter- minate if multiple comparators enable the dac output. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 265 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 register 20-1: cmpconx: comp arator control x register r/w-0 u-0 r/w-0 r-0 r-0 r-0 r-0 r/w-0 cmpon cmpsidl r r r rd a c o e bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r-0 r/w-0 r/w-0 insel1 insel0 extref r cmpstat r cmppol range bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 cmpon: comparator operating mode bit 1 = comparator module is enabled 0 = comparator module is disabled (reduces power consumption) bit 14 unimplemented: read as 0 bit 13 cmpsidl: comparator stop in idle mode bit 1 = discontinues module operation when device enters idle mode. 0 = continues module operation in idle mode if a device has multiple comparators, any cmpsidl bit set to 1 disables all comparators while in idle mode. bit 12-9 reserved: read as 0 bit 8 dacoe: dac output enable 1 = dac analog voltage is output to the dacout pin ( 1 ) 0 = dac analog voltage is not connected to the dacout pin bit 7-6 insel<1:0>: input source select for comparator bits 00 = selects cmpxa input pin 01 = selects cmpxb input pin 10 = selects cmpxc input pin 11 = selects cmpxd input pin bit 5 extref: enable external reference bit 1 = external source provides reference to the dac (maximum dac voltage determined by the external voltage source) 0 = internal reference sources provide reference to the dac (maximum dac voltage determined by the range bit setting) bit 4 reserved: read as 0 bit 3 cmpstat: current state of comparator output including cmppol selection bit bit 2 reserved: read as 0 bit 1 cmppol: comparator output polarity control bit 1 = output is inverted 0 = output is non-inverted bit 0 range: selects dac output voltage range bit 1 = high range: max dac value = av dd /2, 1.65v at 3.3v av dd 0 = low range: max dac value = intref ( 2 ) note 1: dacout can be associated only with a single comparator at any given time. the software must ensure that multiple comparators do not enable the dac output by setting their respective dacoe bit. 2: refer to the dac module specifications ( table 24-43 ) in section 24.0 electrical characteristics for the intref value. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 266 ? 2008-2014 microchip technology inc. register 20-2: cmpdacx: comparator dac x control register r-0 r-0 r-0 r-0 r-0 r-0 r/w-0 r/w-0 r r r r r rc m r e f < 9 : 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmref<7:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 reserved: read as 0 bit 9-0 cmref<9:0>: comparator reference voltage select bits 1111111111 = (cmref<9:0> * intref/1024) or (cmref<9:0> * (av dd /2)/1024) volts depending on the range bit or (cmref<9:0> * extref/1024) if extref is set 0000000000 = 0.0 volts downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 267 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 21.0 special features dspic33fj06gs101/x02 a nd dspic33fj16gsx02/x04 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: flexible configuration watchdog timer (wdt) code protection and codeguard? security jtag boundary scan interface in-circuit serial programming? (icsp?) in-circuit emulation brown-out reset (bor) 21.1 configuration bits dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices provide nonvolatile memory implementations for device configuration bits. refer to device config- uration (ds70194) in the ?dspic33f/pic24h family reference manual? for more information on this implementation. the configuration bits can be programmed (read as 0 ), or left unprogrammed (read as 1 ), to select various device configurations. these bits are mapped starting at program memory location 0xf80000. the individual configuration bit descriptions for the configuration registers are shown in table 21-2 . note that address, 0xf80000, is beyond the user pro- gram memory space. it belongs to the configuration memory space (0x800000-0xffffff), which can only be accessed using table reads and table writes. the device configuration register map is shown in table 21-1 . note 1: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?dspic33f/pic24h family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest ?dspic33f/pic24h family reference manual? sections. 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. table 21-1: device conf iguration register map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xf80000 fbs bss2 bss1 bss0 bwrp 0xf80002 reserved 0xf80004 fgs g s s 1g s s 0g w r p 0xf80006 foscsel ieso fnosc2 fnosc1 fnosc0 0xf80008 fosc fcksm1 fcksm0 iol1way osciofnc poscmd1 poscmd0 0xf8000a fwdt fwdten windis wdtpre wdtpost3 wdtpost2 wdtpost1 wdtpost0 0xf8000c fpor reserved ( 2 ) fpwrt2 fpwrt1 fpwrt0 0xf8000e ficd reserved ( 1 ) jtagen ics1 ics0 0xf80010 fuid0 user unit id byte 0 0xf80012 fuid1 user unit id byte 1 legend: = unimplemented bit, read as 0 . note 1: these bits are reserved for use by development tools and must be programmed to 1 . 2: this bit reads the current programmed value. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 268 ? 2008-2014 microchip technology inc. table 21-2: dspic33f config uration bits description bit field register rtsp effect description bwrp fbs immediate boot segment program flash write protection bit 1 = boot segment can be written 0 = boot segment is write-protected bss<2:0> fbs immediate boot segment program flash code protection size bits x11 = no boot program flash segment boot space is 256 instruction words (except interrupt vectors): 110 = standard security; boot program flash segment ends at 0x0003fe 010 = high security; boot program flash segment ends at 0x0003fe boot space is 768 instruction words (except interrupt vectors): 101 = standard security; boot program flash segment ends at 0x0007fe 001 = high security; boot program flash segment ends at 0x0007fe boot space is 1792 instruction words (except interrupt vectors): 100 = standard security; boot program flash segment ends at 0x000ffe 000 = high security; boot program flash segment ends at 0x000ffe gss<1:0> fgs immediate general segment code-protect bits 11 = user program memory is not code-protected 10 = standard security 0x = high security gwrp fgs immediate general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected ieso foscsel immediate two-speed oscillator start-up enable bit 1 = start-up device with frc, then automatically switch to the user-selected oscillator source when ready 0 = start-up device with user-selected oscillator source fnosc<2:0> foscsel if clock switch is enabled, rtsp effect is on any device reset; otherwise, immediate initial oscillator source selection bits 111 = internal fast rc (frc) oscillator with postscaler 110 = internal fast rc (frc) oscillator with divide-by-16 101 = lprc oscillator 100 = reserved 011 = primary (xt, hs, ec) oscillator with pll 010 = primary (xt, hs, ec) oscillator 001 = internal fast rc (frc) oscillator with pll 000 = frc oscillator fcksm<1:0> fosc immediate clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way fosc immediate peripheral pin select configuration bit 1 = allows only one reconfiguration 0 = allows multiple reconfigurations osciofnc fosc immediate osc2 pin function bit (except in xt and hs modes) 1 = osc2 is the clock output 0 = osc2 is the general purpose digital i/o pin downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 269 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 poscmd<1:0> fosc immediate primary oscillator mode select bits 11 = primary oscillator is disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode fwdten fwdt immediate watchdog timer enable bit 1 = watchdog timer is always enabled (lprc oscillator cannot be disabled; clearing the swdten bit in the rcon register will have no effect) 0 = watchdog timer is enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) windis fwdt immediate watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode wdtpre fwdt immediate watchdog timer prescaler bit 1 = 1:128 0 = 1:32 wdtpost<3:0> fwdt immediate watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 0001 = 1:2 0000 = 1:1 fpwrt<2:0> fpor immediate power-on reset timer value select bits 111 = pwrt = 128 ms 110 = pwrt = 64 ms 101 = pwrt = 32 ms 100 = pwrt = 16 ms 011 = pwrt = 8 ms 010 = pwrt = 4 ms 001 = pwrt = 2 ms 000 = pwrt = disabled jtagen ficd immediate jtag enable bit 1 = jtag is enabled 0 = jtag is disabled ics<1:0> ficd immediate icd communication channel select enable bits 11 = communicates on pgec1 and pged1 10 = communicates on pgec2 and pged2 01 = communicates on pgec3 and pged3 00 = reserved, do not use. table 21-2: dspic33f configuration bits description (continued) bit field register rtsp effect description downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 270 ? 2008-2014 microchip technology inc. 21.2 on-chip voltage regulator the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices power their core digital logic at a nominal 2.5v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 families incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. when the regulator is enabled, a low-esr (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the v cap pin ( figure 21-1 ). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in table 24-13 located in section 24.1 dc characteristics . on a por , it takes approximately 20 ? s for the on-chip voltage regulator to generate an output voltage. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down. figure 21-1: conne ctions for the on-chip voltage regulator ( 1 , 2 , 3 ) 21.3 bor: brown-out reset the brown-out reset (bor) module is based on an internal voltage reference circuit. the main purpose of the bor module is to generate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). a bor generates a reset pulse, which resets the device. the bor selects the clock source, based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is 1 . concurrently, the pwrt time-out (t pwrt ) is applied before the internal reset is released. if t pwrt = 0 and a crystal oscillator is being used, then a nominal delay of t fscm = 100 is applied. the total delay in this case is t fscm . the bor status bit (rcon<1>) is set to indicate that a bor has occurred. the bor circuit continues to operate while in sleep or idle modes and resets the device should v dd fall below the bor threshold voltage. note: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. note 1: these are typical operating voltages. refer to table 24-13 located in section 24.1 dc characteristics for the full operating ranges of v dd . 2: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. 3: typical v cap pin voltage = 2.5v when v dd ? v ddmin . v dd v cap v ss dspic33f c efc 3.3v 10 f tantalum downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 271 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 21.4 watchdog timer (wdt) for the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. 21.4.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>) which allow the selection of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: on any device reset on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc<2:0> bits) or by hardware (i.e., fail-safe clock monitor) when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) when the device exits sleep or idle mode to resume normal operation by a clrwdt instruction during normal execution 21.4.2 sleep and idle modes if the wdt is enabled, it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake the device and code execution will continue from where the pwrsav instruction was executed. the corresponding sleep bit (rcon<3>) or idle bit (rcon<2>) will need to be cleared in software after the device wakes up. 21.4.3 enabling wdt the wdt is enabled or disabled by the fwdten configuration bit in the fwdt configuration register. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to 0 . the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power savings. the wdt flag bit, wdto (rcon<4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. figure 21-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. note: if the windis bit (fwdt<6>) is cleared, the clrwdt instruction should be executed by the application software only during the last 1/4 of the wdt period. this clrwdt window can be determined by using a timer. if a clrwdt instruction is executed before this window, a wdt reset occurs. all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide-by-n1) postscaler (divide-by-n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten fwdten lprc clock rs rs wake-up reset downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 272 ? 2008-2014 microchip technology inc. 21.5 jtag interface the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices implement a jtag interface, which supports boundary scan device testing. detailed information on this interface will be provided in future revisions of the document. 21.6 in-circuit serial programming the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 family of digital signal controllers can be serially programmed while in the end application circuit. this is done with two lines for clock and data and three other lines for power, ground and the programming sequence. serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the ?dspic33f/pic24h flash programming specification? (ds70152) for details about in-circuit serial programming (icsp). any of the three pairs of programming clock/data pins can be used: pgec1 and pged1 pgec2 and pged2 pgec3 and pged3 21.7 in-circuit debugger the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices provide simple debugging functionality through the pgecx (emula- tion/debug clock) and pgedx (emulation/debug data) pin functions. any of the three pairs of debugging clock/data pins can be used: pgec1 and pged1 pgec2 and pged2 pgec3 and pged3 to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , and the pgecx/pgedx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 273 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 21.8 code protection and codeguard? security the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices offer the intermediate implementation of codeguard? security. codeguard security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. this feature helps protect individual intellectual property (ip) in collaborative system designs. when coupled with software encryption libraries, code- guard? security can be used to securely update flash even when multiple ips reside on a single chip. table 21-3: code flash security segment sizes for 6-kbyte devices the code protection features are controlled by the configuration registers: fbs and fgs. secure segment and ram protection is not implemented in dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices. table 21-4: code flash security segment sizes for 16-kbyte devices configuration bits bss<2:0> = x11 0k bss<2:0> = x10 256 bss<2:0> = x01 768 bss<2:0> = x00 1792 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h gs = 1792 iw 000ffeh 001000h 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h 000ffeh 001000h gs = 1536 iw bs = 256 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h 000ffeh 001000h gs = 1024 iw bs = 768 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h 000ffeh 001000h bs = 1792 iw note: refer to codeguard? security (ds70199) for further information on codeguard security usage, configuration and operation. configuration bits bss<2:0> = x11 0k bss<2:0> = x10 256 bss<2:0> = x01 768 bss<2:0> = x00 1792 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h gs = 5376 iw 000ffeh 001000h 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h 000ffeh 001000h gs = 5120 iw bs = 256 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h 000ffeh 001000h gs = 4608 iw bs = 768 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0003feh 000400h 0007feh 000800h gs = 3584 iw 000ffeh 001000h bs = 1792 iw downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 274 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 275 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 22.0 instruction set summary the dspic33f instruction set is identical to that of the dspic30f. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: word or byte-oriented operations bit-oriented operations literal operations dsp operations control operations table 22-1 shows the general symbols used in describing the instructions. the dspic33f instruction set summary in tab l e 2 2- 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: the first source operand, which is typically a register wb without any address modifier the second source operand, which is typically a register ws with or without an address modifier the destination of the result, which is typically a register wd with or without an address modifier however, word or byte-oriented file register instructions have two operands: the file register specified by the value, f the destination, which could be either the file register, f, or the w0 register, which is denoted as wreg most bit-oriented instructions (including simple rotate/shift instructions) have two operands: the w register (with or without an address modifier) or file register (specified by the value of ws or f) the bit in the w register or file register (specified by a literal value or indirectly by the contents of register wb) the literal instructions that involve data movement can use some of the following operands: a literal value to be loaded into a w register or file register (specified by k) the w register or file register where the literal value is to be loaded (specified by wb or f) however, literal instructions that involve arithmetic or logical operations use some of the following operands: the first source operand, which is a register wb without any address modifier the second source operand, which is a literal value the destination of the result (only if not the same as the first source operand), which is typically a register wd with or without an address modifier the mac class of dsp instructions can use some of the following operands: the accumulator (a or b) to be used (required operand) the w registers to be used as the two operands the x and y address space prefetch operations the x and y address space prefetch destinations the accumulator write-back destination the other dsp instructions do not involve any multiplication and can include: the accumulator to be used (required) the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier the amount of shift specified by a w register, wn, or a literal value the control instructions can use some of the following operands: a program memory address the mode of the table read and table write instructions note: this data sheet summarizes the features of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the latest sections in the ?dspic33f/pic24h family reference manual? , which are available on the microchip web site ( www.microchip.com ). downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 276 ? 2008-2014 microchip technology inc. most instructions are a single word. certain double-word instructions are designed to provide all the required information in these 48 bits. in the second word, the 8 msbs are 0 s. if this second word is executed as an instruction (by itself), it will execute as a nop . the double-word instructions execute in two instruction cycles. most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (unconditional/computed branch), indirect call/goto , all table reads and table writes and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. note: for more details on the instruction set, refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157). table 22-1: symbols used in opcode descriptions field description #text means literal defined by text (text) means content of text [text] means the location addressed by text { } optional field or operation ? 2008-2014 microchip technology inc. ds70000318g-page 277 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 wm*wm multiplicand and multiplier working register pair for square instructions ?? {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wm*wn multiplicand and multiplier working register pair for dsp instructions ? {w4 * w5,w4 * w6,w4 * w7,w5 * w6,w5 * w7,w6 * w7} wn one of 16 working registers ?? {w0..w15} wnd one of 16 destination working registers ?? {w0...w15} wns one of 16 source working registers ?? {w0...w15} wreg w0 (working register used in file register instructions) ws source w register ?? { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register ?? { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions ? {[w8] + = 6, [w8] + = 4, [w8] + = 2, [w8], [w8] - = 6, [w8] - = 4, [w8] - = 2, [w9] + = 6, [w9] + = 4, [w9] + = 2, [w9], [w9] - = 6, [w9] - = 4, [w9] - = 2, [w9 + w12], none} wxd x data space prefetch destination register for dsp instructions ?? {w4...w7} wy y data space prefetch address register for dsp instructions ? {[w10] + = 6, [w10] + = 4, [w10] + = 2, [w10], [w10] - = 6, [w10] - = 4, [w10] - = 2, [w11] + = 6, [w11] + = 4, [w11] + = 2, [w11], [w11] - = 6, [w11] - = 4, [w11] - = 2, [w11 + w12], none} wyd y data space prefetch destination register for dsp instructions ?? {w4...w7} table 22-1: symbols used in opcode descriptions (continued) field description downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 278 ? 2008-2014 microchip technology inc. table 22-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumulator a overflow 1 1 (2) none bra ob,expr branch if accumulator b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumulator a saturated 1 1 (2) none bra sb,expr branch if accumulator b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws ? 2008-2014 microchip technology inc. ds70000318g-page 279 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 280 ? 2008-2014 microchip technology inc. 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 divf divf wm,wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 31 do do #lit14,expr do code to pc + expr, lit14 + 1 times 2 2 none do wn,expr do code to pc + expr, (wn) + 1 times 2 2 none 32 ed ed wm*wm,acc,wx,wy,wxd euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 33 edac edac wm*wm,acc,wx,wy,wxd euclidean distance 1 1 oa,ob,oab, sa,sb,sab 34 exch exch wns,wnd swap wns with wnd 1 1 none 35 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 36 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 37 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 38 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 39 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 40 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 41 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 42 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 43 lnk lnk #lit14 link frame pointer 1 1 none 44 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 45 mac mac wm*wn,acc,wx,wxd,wy,wyd ,awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 46 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 none mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 none mov.d wns,wd move double from w(ns):w(ns + 1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 1 2 none 47 movsac movsac acc,wx,wxd,wy,wyd,awb prefetch and store accumulator 1 1 none table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 281 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 48 mpy mpy wm*wn,acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 49 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd -(multiply wm by wn) to accumulator 1 1 none 50 msc msc wm*wm,acc,wx,wxd,wy,wyd ,awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 51 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 11 n o n e mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 11 n o n e mul f w3:w2 = f * wreg 1 1 none 52 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 53 nop nop no operation 1 1 none nopr no operation 1 1 none 54 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 12 n o n e pop.s pop shadow registers 1 1 all 55 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 56 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 57 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 58 repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 59 reset reset software device reset 1 1 none 60 retfie retfie return from interrupt 1 3 (2) none 61 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 62 return return return from subroutine 1 3 (2) none 63 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 64 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 65 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 282 ? 2008-2014 microchip technology inc. 66 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 67 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 68 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 69 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 70 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab 71 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 72 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f C wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f C wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn C lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb C ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb C lit5 1 1 c,dc,n,ov,z 73 subb subb f f = f C wreg C (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f C wreg C (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn C lit10 C (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb C ws C (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb C lit5 C (c ) 1 1 c,dc,n,ov,z 74 subr subr f f = wreg C f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg C f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws C wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 C wb 1 1 c,dc,n,ov,z 75 subbr subbr f f = wreg C f C (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg C f C (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws C wb C (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 C wb C (c ) 1 1 c,dc,n,ov,z 76 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 77 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 78 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 79 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 80 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 81 ulnk ulnk unlink frame pointer 1 1 none 82 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 83 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 283 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 23.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: integrated development environment - mplab ? x ide software compilers/assemblers/linkers - mplab xc compiler - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families simulators - mplab x sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 device programmers - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits and starter kits third-party development tools 23.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: color syntax highlighting smart code completion makes suggestions and provides hints as you type automatic code formatting based on user-defined rules live parsing user-friendly, customizable interface: fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. call graph window project-based workspaces: multiple projects multiple tools multiple configurations simultaneous debugging sessions file history and bug tracking: local file history feature built-in support for bugzilla issue tracker downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 284 ? 2008-2014 microchip technology inc. 23.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchips 8, 16 and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an exe- cutable file. mplab xc compiler uses the assembler to produce its object file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility 23.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: integration into mplab x ide projects user-defined macros to streamline assembly code conditional assembly for multipurpose source files directives that allow complete control over the assembly process 23.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 23.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 285 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 23.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 23.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 23.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchips most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineers pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 23.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineers pc using a full- speed usb interface and can be connected to the target via a microchip debug (rj-11) connector (com- patible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 23.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 286 ? 2008-2014 microchip technology inc. 23.11 demonstration/development boards, evaluation kits and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 23.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. device programmers and gang programmers from companies, such as softlog and ccs software tools from companies, such as gimpel and trace systems protocol analyzers from companies, such as saleae and total phase demonstration boards from companies, such as mikroelektronika, digilent ? and olimex embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ? downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 287 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 24.0 electrical characteristics this section provides an overview of dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 electrical characteristi cs. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings ( 1 ) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss ( 3 ) ................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss , when v dd ? 3.0v ( 3 ) ................................................. -0.3v to +5.6v voltage on any 5v tolerant pin with respect to vss, when v dd < 3.0v ( 3 ) ........................................ -0.3v to (v dd + 0.3v) maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ( 2 ) ...........................................................................................................................250 ma maximum current sourced/sunk by any 4x i/o pin ................................................................................. .................15 ma maximum current sourced/sunk by any 8x i/o pin ................................................................................. .................25 ma maximum current sourced/sunk by any 16x i/o pin ................................................................................ ................45 ma maximum current sunk by all ports .......................................................................................................................200 ma maximum current sourced by all ports ( 2 ) ...............................................................................................................200 ma note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at those or any other con ditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see tab l e 2 4- 2 ). 3: see the pin diagrams section for 5v tolerant pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 288 ? 2008-2014 microchip technology inc. 24.1 dc characteristics table 24-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) max mips dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 3.0-3.6v ( 1 ) -40c to +85c 40 3.0-3.6v ( 1 ) -40c to +125c 40 note 1: overall functional device operation at v bormin < v dd < v ddmin is tested but not characterized. all device analog modules such as the adc, etc., will function but with degraded performance below v ddmin . refer to parameter bo10 in table 24-11 for bor values. table 24-2: thermal operating conditions rating symbol min typ max unit industrial temperature devices operating junction temperature range t j -40 +125 c operating ambient temperature range t a -40 +85 c extended temperature devices operating junction temperature range t j -40 +140 c operating ambient temperature range t a -40 +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? ? i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ? ({v dd ? v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t j C t a )/ ? ja w table 24-3: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistance, 44-pin qfn ? ja 28 c/w 1 package thermal resistance, 44-pin tfqp ? ja 39 c/w 1 package thermal resistance, 28-pin spdip ? ja 42 c/w 1 package thermal resistance, 28-pin soic ? ja 47 c/w 1 package thermal resistance, 28-pin qfn-s ? ja 34 c/w 1 package thermal resistance, 18-pin soic ? ja 57 c/w 1 package thermal resistance, 44-pin vtla ? ja 25 c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 289 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions operating voltage dc10 v dd supply voltage ( 4 ) 3.0 3.6 v industrial and extended dc12 v dr ram data retention voltage ( 2 ) 1.8 v dc16 v por v dd start voltage to ensure internal power-on reset signal v ss v dc17 sv dd v dd rise rate ( 3 ) to ensure internal power-on reset signal 0.03 v/ms 0v-3.0v in 0.1 seconds note 1: data in typ column is at 3.3v, +25c unless otherwise stated. 2: this is the limit to which v dd may be lowered without losing ram data. 3: these parameters are characterized but not tested in manufacturing. 4: overall functional device operation at v bormin < v dd < v ddmin is tested but not characterized. all device analog modules such as the adc, etc., will function but with degraded performance below v ddmin . refer to parameter bo10 in table 24-11 for bor values. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 290 ? 2008-2014 microchip technology inc. table 24-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions operating current (i dd ) ( 2 ) dc20d 55 70 ma -40c 3.3v 10 mips see note 2 dc20a 55 70 ma +25c dc20b 55 70 ma +85c dc20c 55 70 ma +125c dc21d 68 85 ma -40c 3.3v 16 mips see note 2 and note 3 dc21a 68 85 ma +25c dc21b 68 85 ma +85c dc21c 68 85 ma +125c dc22d 78 95 ma -40c 3.3v 20 mips see note 2 and note 3 dc22a 78 95 ma +25c dc22b 78 95 ma +85c dc22c 78 95 ma +125c dc23d 88 110 ma -40c 3.3v 30 mips see note 2 and note 3 dc23a 88 110 ma +25c dc23b 88 110 ma +85c dc23c 88 110 ma +125c dc24d 98 120 ma -40c 3.3v 40 mips see note 2 dc24a 98 120 ma +25c dc24b 98 120 ma +85c dc24c 98 120 ma +125c dc25d 128 160 ma -40c 3.3v 40 mips see note 2 , except pwm is operating at maximum speed (ptcon2 = 0x0000) dc25a 125 150 ma +25c dc25b 121 150 ma +85c dc25c 119 150 ma +125c dc26d 115 140 ma -40c 3.3v 40 mips see note 2 , except pwm is operating at 1/2 speed (ptcon2 = 0x0001) dc26a 112 140 ma +25c dc26b 110 140 ma +85c dc26c 108 140 ma +125c note 1: data in typical column is at 3.3v, +25c unless otherwise stated. 2: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: oscillator is configured in ec mode with pll, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) cpu executing while(1) statement jtag disabled 3: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 291 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 dc27d 111 140 ma -40c 3.3v 40 mips see note 2 , except pwm is operating at 1/4 speed (ptcon2 = 0x0002) dc27a 108 130 ma +25c dc27b 105 130 ma +85c dc27c 103 130 ma +125c dc28d 102 130 ma -40c 3.3v 40 mips see note 2 , except pwm is operating at 1/8 speed (ptcon2 = 0x0003) dc28a 100 120 ma +25c dc28b 100 120 ma +85c dc28c 100 120 ma +125c table 24-5: dc characteristics: operating current (i dd ) (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions operating current (i dd ) ( 2 ) note 1: data in typical column is at 3.3v, +25c unless otherwise stated. 2: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: oscillator is configured in ec mode with pll, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) cpu executing while(1) statement jtag disabled 3: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 292 ? 2008-2014 microchip technology inc. table 24-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions idle current (i idle ): core off clock on base current ( 2 ) dc40d 48 ma -40c 3.3v 10 mips dc40a 48 ma +25c dc40b 48 ma +85c dc40c 48 ma +125c dc41d 60 ma -40c 3.3v 16 mips ( 3 ) dc41a 60 ma +25c dc41b 60 ma +85c dc41c 60 ma +125c dc42d 68 ma -40c 3.3v 20 mips ( 3 ) dc42a 68 ma +25c dc42b 68 ma +85c dc42c 68 ma +125c dc43d 77 ma -40c 3.3v 30 mips ( 3 ) dc43a 77 ma +25c dc43b 77 ma +85c dc43c 77 ma +125c dc44d 86 ma -40c 3.3v 40 mips dc44a 86 ma +25c dc44b 86 ma +85c dc44c 86 ma +125c note 1: data in typical column is at 3.3v, +25c unless otherwise stated. 2: base idle current (i idle ) is measured as follows: cpu core is off, oscillator is configured in ec mode and external clock is active, osc1 is driv en with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) jtag is disabled 3: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 293 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions power-down current (i pd ) ( 2 , 4 ) dc60d 125 500 ? a- 4 0 c 3.3v base power-down current dc60a 135 500 ? a+ 2 5 c dc60b 235 500 ? a+ 8 5 c dc60c 565 950 ? a +125c dc61d 40 50 ? a- 4 0 c 3.3v watchdog timer current: ? i wdt ( 3 ) dc61a 40 50 ? a+ 2 5 c dc61b 40 50 ? a+ 8 5 c dc61c 80 90 ? a +125c note 1: data in the typical column is at 3.3v, +25c unless otherwise stated. 2: i pd (sleep) current is measured as follows: cpu core is off, oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled all peripheral modules are disabled (pmdx bits are all ones) the vregs bit (rcon<8>) = 0 (i.e., core regulator is set to stand-by while the device is in sleep mode) jtag disabled 3: the ? current is the additional current consumed when the wdt module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device containing the most memory in this family. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 294 ? 2008-2014 microchip technology inc. table 24-8: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max doze ratio units conditions doze current (i doze ) ( 2 ) dc73a 75 105 1:2 ma -40c 3.3v 40 mips dc73f 60 105 1:64 ma dc73g 60 105 1:128 ma dc70a 75 105 1:2 ma +25c 3.3v 40 mips dc70f 60 105 1:64 ma dc70g 60 105 1:128 ma dc71a 75 105 1:2 ma +85c 3.3v 40 mips dc71f 60 105 1:64 ma dc71g 60 105 1:128 ma dc72a 75 105 1:2 ma +125c 3.3v 40 mips dc72f 60 105 1:64 ma dc72g 60 105 1:128 ma note 1: data in the typical column is at 3.3v, +25c unless otherwise stated. 2: i doze is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i doze measurements are as follows: oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) cpu executing while(1) statement jtag disabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 295 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions v il input low voltage di10 i/o pins v ss 0.2v dd v di15 mclr v ss 0.2v dd v di16 i/o pins with osc1 v ss 0.2v dd v di18 i/o pins with sdax, sclx v ss 0.3 v dd v smbus disabled di19 i/o pins with sdax, sclx v ss 0.8 v smbus enabled v ih input high voltage di20 di21 i/o pins not 5v tolerant ( 4 ) i/o pins 5v tolerant ( 4 ) 0.7 v dd 0.7 v dd v dd 5.5 vv di28 di29 sda1, scl1 sda1, scl1 0.7 v dd 2.1 5.5 5.5 vv smbus disabled smbus enabled i cnpu cnx pull-up current di30 250 ? av dd = 3.3v, v pin = v ss i il input leakage current ( 2 , 3 , 4 ) di50 i/o pins with: 4x driver pins - ra0-ra2, rb0-rb2, rb5-rb10, rb15, rc1, rc2, rc9, rc10 8x driver pins - rc0, rc3-rc8, rc11-rc13 16x driver pins - ra3, ra4, rb3, rb4, rb11-rb14 2 4 8 ? a ? a ? a v ss ? v pin ? v dd , pin at high-impedance v ss ? v pin ? v dd , pin at high-impedance v ss ? v pin ? v dd , pin at high-impedance di55 mclr 2 ? av ss ?? v pin ?? v dd di56 osc1 2 ? av ss ?? v pin ?? v dd , xt and hs modes note 1: data in typ column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see pin diagrams for the list of 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any positive input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical absolute instantaneous sum of the input injection currents from all pins do no t exceed the specified limit. characterized but not tested. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 296 ? 2008-2014 microchip technology inc. i icl input low injection current di60a 0 -5 ( 5 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap and rb5 i ich input high injection current di60b 0 +5 ( 6 , 7 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , rb5 and digital 5v-tolerant designated pins ?? i ict total input injection current di60c (sum of all i/o and control pins) -20 ( 9 ) + 2 0 ( 9 ) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) ? ?? i ict table 24-9: dc characteristics: i/o pi n input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions note 1: data in typ column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see pin diagrams for the list of 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any positive input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical absolute instantaneous sum of the input injection currents from all pins do no t exceed the specified limit. characterized but not tested. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 297 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-10: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. symbol characteristic min. typ. max. units conditions do10 v ol output low voltage i/o pins: 4x sink driver pins C ra0-ra2, rb0-rb2, rb5-rb10, rb15, rc1, rc2, rc9, rc10 0 . 4v i ol ? 6 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 8x sink driver pins C rc0, rc3-rc8, rc11-rc13 0 . 4v i ol ? 10 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 16x sink driver pins C ra3, ra4, rb3, rb4, rb11-rb14 0 . 4v i ol ? 18 ma, v dd = 3.3v see note 1 do20 v oh output high voltage i/o pins: 4x source driver pins C ra0-ra2, rb0-rb2, rb5- rb10, rb15, rc1, rc2, rc9, rc10 2.4 v i oh ? -6 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins C rc0, rc3-rc8, rc11-rc13 2.4 v i oh ? -10 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 16x source driver pins C ra3, ra4, rb3, rb4, rb11-rb14 2.4 v i oh ? -18 ma, v dd = 3.3v see note 1 do20a v oh 1 output high voltage i/o pins: 4x source driver pins C ra0-ra2, rb0-rb2, rb5-rb10, rb15, rc1, rc2, rc9, rc10 1.5 v i oh ? -12 ma, v dd = 3.3v see note 1 2.0 i oh ? -11 ma, v dd = 3.3v see note 1 3.0 i oh ? -3 ma, v dd = 3.3v see note 1 output high voltage 8x source driver pins C rc0, rc3-rc8, rc11-rc13 1.5 v i oh ? -16 ma, v dd = 3.3v see note 1 2.0 i oh ? -12 ma, v dd = 3.3v see note 1 3.0 i oh ? -4 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 16x source driver pins C ra3, ra4, rb3, rb4, rb11-rb14 1.5 v i oh ? -30 ma, v dd = 3.3v see note 1 2.0 i oh ? -25 ma, v dd = 3.3v see note 1 3.0 i oh ? -8 ma, v dd = 3.3v see note 1 note 1: parameters are characterized, but not tested. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 298 ? 2008-2014 microchip technology inc. table 24-11: electrical characteristics: bor dc characteristics standard operating conditions (see note 3 ): 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min ( 1 ) typ max units conditions bo10 v bor bor event on v dd transition high-to-low bor event is tied to v dd core voltage decrease 2.55 2.79 v see note 2 note 1: parameters are for design guidance only and are not tested in manufacturing. 2: the device will operate as normal until the v ddmin threshold is reached. 3: overall functional device operation at v bormin < v dd < v ddmin is tested but not characterized. all device analog modules such as the adc, etc., will function but with degraded performance below v ddmin . downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 299 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-13: internal voltag e regulator specifications table 24-12: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions program flash memory d130 e p cell endurance 10,000 e/w -40 ? c to +125 ? c d131 v pr v dd for read v min 3 . 6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min 3 . 6vv min = minimum operating voltage d134 t retd characteristic retention 20 year provided no other specifications are violated, -40 ? c to +125 ? c d135 i ddp supply current during programming 1 0 m a d136a t rw row write time 1.477 1.538 ms t rw = 11064 frc cycles, t a = +85c, see note 2 d136b t rw row write time 1.435 1.586 ms t rw = 11064 frc cycles, t a = +125c, see note 2 d137a t pe page erase time 22.5 23.4 ms t pe = 168517 frc cycles, t a = +85c, see note 2 d137b t pe page erase time 21.9 24.2 ms t pe = 168517 frc cycles, t a = +125c, see note 2 d138a t ww word write cycle time 47.4 49.3 s t ww = 355 frc cycles, t a = +85c, see note 2 d138b t ww word write cycle time 46 50.9 s t ww = 355 frc cycles, t a = +125c, see note 2 note 1: data in typ column is at 3.3v, +25c unless otherwise stated. 2: other conditions: frc = 7.37 mhz, tun<5:0> = b'011111 (for min), tun<5:0> = b'100000 (for max). this parameter depends on the frc accuracy (see table 24-20 ) and the value of the frc oscillator tun- ing register (see register 9-4 ). for complete details on calculating the minimum and maximum time see section 5.3 programming operations . operating conditions: -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristics min typ max units comments c efc external filter capacitor value ( 1 ) 4.7 10 ? f capacitor must be low series resistance (< 5 ohms) note 1: typical v cap voltage = 2.5 volts when v dd ? v ddmin . downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 300 ? 2008-2014 microchip technology inc. 24.2 ac characteristics and timing parameters this section defines dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ac characteristics and timing parameters. table 24-14: temperature and vo ltage specifications C ac figure 24-1: load conditions for device timing specifications table 24-15: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended operating voltage v dd range as described in table 24-1 . param no. symbol characteristic min typ max units conditions do50 c osco osc2 pin 15 pf in xt and hs modes when external clock is used to drive osc1 do56 c io all i/o pins and osc2 50 pf ec mode do58 c b sclx, sdax 400 pf in i 2 c? mode v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 C for all pins except osc2 load condition 2 C for osc2 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 301 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-2: external clock timing q1 q2 q3 q4 osc1 clko q1 q2 q3 q4 os20 os25 os30 os30 os40 os41 os31 os31 table 24-16: external clo ck timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symb characteristic min typ ( 1 ) max units conditions os10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc 40 mhz ec oscillator crystal frequency 3.5 10 1040 mhzmhz xths os20 t osc t osc = 1/f osc 12.5 dc ns os25 t cy instruction cycle time ( 2 ) 25 dc ns os30 tosl, to s h external clock in (osc1) high or low time 0.375 x t osc 0.625 x t osc ns ec os31 tosr, to s f external clock in (osc1) rise or fall time 20 ns ec os40 tckr clko rise time ( 3 ) 5 . 2n s os41 tckf clko fall time ( 3 ) 5 . 2n s os42 g m external oscillator transconductance ( 4 ) 14 16 18 ma/v v dd = 3.3v, t a = +25oc note 1: data in typ column is at 3.3v, +25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at min. values with an external clock applied to the osc1/clki pin. when an external clock input is used, the max. cycle time limit is dc (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osc2 pin. 4: data for this parameter is preliminary. this parameter is characterized, but not tested in manufacturing. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 302 ? 2008-2014 microchip technology inc. table 24-17: pll clock timing specifications (v dd = 3.0v to 3.6v) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 0.8 8 mhz ecpll, xtpll modes os51 f sys on-chip vco system frequency 100 200 mhz os52 t lock pll start-up time (lock time) 0.9 1.5 3.1 ms os53 d clk clko stability (jitter) ( 2 ) -3 0.5 3 % measured over 100 ms period note 1: data in typ column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested in manufacturing. 2: these parameters are characterized by similarity, but are not tested in manufacturing. this specificati on is based on clock cycle by clock cycle measurements. to calculate the effective jitter for individ ual time bases or communication clocks use this formula: table 24-18: auxiliary pll clock timing specifications (v dd = 3.0v to 3.6v) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions os56 f hpout on-chip 16x pll cco frequency 112 118 120 mhz os57 f hpin on-chip 16x pll phase detector input frequency 7.0 7.37 7.5 mhz os58 t su frequency generator lock time 1 0 s note 1: data in typ column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested in manufacturing. peripheral clock jitter d clk f osc peripheral bit rate clock -------------------------------------------------------------- ?? ?? ----------------------------------------------------------------------- - = for example: f osc = 32 mhz, d clk = 3%, spi bit rate clock (i.e., sckx) is 2 mhz. spi sck jitter d clk 32 mhz 2 mhz -------------------- ?? ?? ----------------------------- - 3% 16 --------- - 3% 4 ------- - 0.75% == = = downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 303 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-19: ac characteristics: internal frc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ?? +85c for industrial -40c ? t a ? +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ frc frequency = 7.37 mhz ( 1 ) f20a frc -2 +2 % -40c ? t a ?? +85c v dd = 3.0-3.6v f20b frc -5 +5 % -40c ? t a ?? +125c v dd = 3.0-3.6v note 1: frequency calibrated at +25c and 3.3v. tunx bits can be used to compensate for temperature drift. table 24-20: ac characteristics: internal lprc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. characteristic min typ max units conditions lprc @ 32.768 khz ( 1 ) f21a lprc -20 6 +20 % -40c ? t a ?? +85c v dd = 3.0-3.6v f21b lprc -70 +70 % -40c ? t a ?? +125c v dd = 3.0-3.6v note 1: change of lprc frequency as v dd changes. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 304 ? 2008-2014 microchip technology inc. figure 24-3: i/o timing characteristics note: refer to figure 24-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 table 24-21: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v(unless otherwise stated ) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions do31 t io r port output rise time: 4x source driver pins C ra0-ra2, rb0-rb2, rb5-rb10, rb15, rc1, rc2, rc9, rc10 1 02 5n sr e f e r t o figure 24-1 for test conditions 8x source driver pins C rc0, rc3-rc8, rc11-rc13 8 20 ns 16x source driver pins C ra3, ra4, rb3, rb4, rb11-rb14 6 15 ns do32 t io f port output fall time: 4x source driver pins C ra0-ra2, rb0-rb2, rb5-rb10, rb15, rc1, rc2, rc9, rc10 1 02 5n s refer to figure 24-1 for test conditions 8x source driver pins C rc0, rc3-rc8, rc11-rc13 8 20 ns 16x source driver pins C ra3, ra4, rb3, rb4, rb11-rb14 6 15 ns di35 t inp intx pin high or low time (input) 20 ns di40 t rbp cnx high or low time (input) 2 t cy note 1: data in typ column is at 3.3v, +25c unless otherwise stated. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 305 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-4: reset, watchdog timer, os cillator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 24-1 for load conditions. fscm delay sy35 sy30 sy12 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 306 ? 2008-2014 microchip technology inc. table 24-22: reset, watchdog timer, oscill ator start-up timer, power-up timer timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sy10 t mc lm c l r pulse width (low) 2 ? s -40c to +85c sy11 t pwrt power-up timer period 2 48 1632 64 128 ms -40c to +85c, user programmable sy12 t por power-on reset delay 3 10 30 ? s -40c to +85c sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset 0.68 0.72 1.2 ? s sy20 t wdt 1 watchdog timer time-out period ms see section 21.4 watch- dog timer (wdt) and lprc parameter f21a ( table 24-20 ) sy30 t ost oscillator start-up time 1024 t osc t osc = osc1 period note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 307 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-5: timer1, 2 and 3 external cl ock timing characteristics note: refer to figure 24-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 24-23: timer1 external clock timing requirements ( 1 ) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units conditions ta10 t tx h t1ck high time synchronous, no prescaler t cy + 20 ns must also meet parameter ta15, n = prescale value (1, 8, 64, 256) synchronous, with prescaler (t cy + 20)/n ns asynchronous 20 ns ta11 t tx lt 1 c k l o w time synchronous, no prescaler t cy + 20 ns must also meet parameter ta15, n = prescale value (1, 8, 64, 256) synchronous, with prescaler (t cy + 20)/n ns asynchronous 20 ns ta15 t tx p t1ck input period synchronous, no prescaler 2 t cy + 40 ns synchronous, with prescaler greater of: 40 ns or (2 t cy + 40)/n n = prescale value (1, 8, 64, 256) asynchronous 40 ns os60 f t 1 t1ck oscillator input frequency range (oscillator enabled by setting bit, tcs (t1con<1>)) dc 50 khz ta20 t ckextmrl delay from external t1ck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 note 1: timer1 is a type a timer. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 308 ? 2008-2014 microchip technology inc. table 24-24: timer2 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units conditions tb10 t tx h t2ck high time synchronous greater of: 20 ns or (t cy + 20)/n ns must also meet parameter tb15, n = prescale value (1, 8, 64, 256) tb11 t tx l t2ck low time synchronous greater of: 20 ns or (t cy + 20)/n ns must also meet parameter tb15, n = prescale value (1, 8, 64, 256) tb15 t tx p t2ck input period synchronous greater of: 40 ns or (2 t cy + 40)/n ns n = prescale value (1, 8, 64, 256) tb20 t ckextmrl delay from external t2ck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 ns table 24-25: timer3 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ max units conditions tc10 t tx h t3ck high time synchronous t cy + 20 ns must also meet parameter tc15 tc11 t tx lt 3 c k l o w time synchronous t cy + 20 ns must also meet parameter tc15 tc15 t tx p t3ck input period synchronous, with prescaler 2 t cy + 40 ns tc20 t ckextmrl delay from external t3ck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 309 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-6: input capture x (icx ) timing characteristics figure 24-7: output compare x module (ocx) timing characteristics table 24-26: input capture x timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns ic15 tccp icx input period (t cy + 40)/n ns n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. table 24-27: output compare x module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions oc10 tccf ocx output fall time ns see parameter do32 oc11 tccr ocx output rise time ns see parameter do31 note 1: these parameters are characterized but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 24-1 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 24-1 for load conditions. or pwm mode) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 310 ? 2008-2014 microchip technology inc. figure 24-8: ocx/pwmx module timing characteristics ocfa ocx oc15 active tri-state oc20 table 24-28: simple ocx/pwmx mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions oc15 t fd fault input to pwmx i/o change t cy + 20 ns oc20 t flt fault input pulse width t cy + 20 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 311 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-9: high-speed pwmx module fault timing characteristics figure 24-10: high-speed pwmx mo dule timing characteristics fltx pwmx mp20 mp30 pwmx mp11 mp10 note: refer to figure 24-1 for load conditions. table 24-29: high-speed pwmx module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions mp10 t fpwm pwmx output fall time 2.5 ns mp11 t rpwm pwmx output rise time 2.5 ns mp20 t fd fault input ? to pwm i/o change 1 5n s mp30 t fh minimum pwmx fault pulse width 8 ns dtc<1:0> = 10 mp31 t pdly ta p d e l a y 1 . 0 4 n s a clk = 120 mhz mp32 a clk pwmx input clock 120 mhz see note 2 note 1: these parameters are characterized but not tested in manufacturing. 2: this parameter is a maximum allowed input clock for the pwmx module. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 312 ? 2008-2014 microchip technology inc. table 24-30: spix maximu m data/clock rate summary figure 24-11: spix master mode ( half-duplex, transmit only, cke = 0 ) timing characteristics figure 24-12: spix master mode ( half-duplex, transmit only, cke = 1 ) timing characteristics ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 24-31 0 , 10 , 10 , 1 9 mhz table 24-32 10 , 11 9 mhz table 24-33 00 , 11 15 mhz table 24-34 100 11 mhz table 24-35 110 15 mhz table 24-36 010 11 mhz table 24-37 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 24-1 for load conditions. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 24-1 for load conditions. sp36 sp10 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 313 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-31: spix master mode (half-duple x, transmit only) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency 15 mhz see note 3 sp20 tscf sckx output fall time ns see parameter do32 and note 4 sp21 tscr sckx output rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 314 ? 2008-2014 microchip technology inc. figure 24-13: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics table 24-32: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency 9 mhz see note 3 sp20 tscf sckx output fall time ns see parameter do32 and note 4 sp21 tscr sckx output rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 3 0 n s sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 3 0 n s sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 3 0 n s note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 24-1 for load conditions. sp36 sp41 lsb in bit 14 - - - -1 sdix sp40 sp10 msb in downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 315 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-14: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics table 24-33: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency 9 mhz -40oc to +125oc and see note 3 sp20 tscf sckx output fall time ns see parameter do32 and note 4 sp21 tscr sckx output rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 3 0 n s sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 3 0 n s sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 3 0 n s note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 24-1 for load conditions. sp10 msb in downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 316 ? 2008-2014 microchip technology inc. figure 24-15: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp60 sp30, sp31 msb bit 14 - - - - - -1 lsb sp51 bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 24-1 for load conditions. sp50 msb in downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 317 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-34: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency 1 5 m h z s e e note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance (4) 10 50 ns sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge 5 0n s note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 318 ? 2008-2014 microchip technology inc. figure 24-16: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp60 sp30, sp31 msb bit 14 - - - - - -1 lsb sp51 bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 24-1 for load conditions. msb in sp50 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 319 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-35: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency 1 1 m h z s e e note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance (4) 10 50 ns sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge 5 0n s note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 320 ? 2008-2014 microchip technology inc. figure 24-17: spix slave mode (full-duplex cke = 0 , ckp = 1 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30, sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 note: refer to figure 24-1 for load conditions. sdi x sp70 msb in downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 321 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-36: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency 1 5 m h z s e e note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 322 ? 2008-2014 microchip technology inc. figure 24-18: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdox sp50 sp40 sp41 sp30, sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 note: refer to figure 24-1 for load conditions. sdix sp70 msb in downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 323 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-37: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency 1 1 m h z s e e note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 324 ? 2008-2014 microchip technology inc. figure 24-19: i2cx bus start/stop bits ti ming characteristics (master mode) figure 24-20: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition note: refer to figure 24-1 for load conditions. im30 im31 im33 im34 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 24-1 for load conditions. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 325 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-38: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min ( 1 ) max units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 1) ? s 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? s im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 1) ? s 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? s im20 t f : scl sdax and sclx fall time 100 khz mode 300 ns c b is specified to be from 10 pf to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 2 ) 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode 1000 ns c b is specified to be from 10 pf to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 2 ) 300 ns im25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode ( 2 ) 40 ns im26 t hd : dat data input hold time 100 khz mode 0 ? s 400 khz mode 0 0.9 ? s 1 mhz mode ( 2 ) 0.2 ? s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 1) ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 1) ? s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 1) ? s 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? s im34 t hd : sto stop condition 100 khz mode t cy /2 (brg + 1) ns hold time 400 khz mode t cy /2 (brg + 1) ns 1 mhz mode ( 2 ) t cy /2 (brg + 1) ns im40 t aa : scl output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode ( 2 ) 400 ns im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode ( 2 ) 0.5 ? s im50 c b bus capacitive loading 400 pf im51 t pgd pulse gobbler delay 65 390 ns see note 3 note 1: brg is the value of the i 2 c? baud rate generator. refer to inter-integrated circuit (i 2 c?) (ds70000195) in the dspic33/pic24 family reference manual? . 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: typical value for this parameter is 130 ns. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 326 ? 2008-2014 microchip technology inc. figure 24-21: i2cx bus start/stop bits ti ming characteristics (slave mode) figure 24-22: i2cx bus data timing characteristics (slave mode) sclxsdax start condition stop condition is31 is30 is34 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 327 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-39: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz 1 mhz mode ( 1 ) 0.5 ? s is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode ( 1 ) 0.5 ? s is20 t f : scl sdax and sclx fall time 100 khz mode 300 ns c b is specified to be from 10 pf to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 1 ) 100 ns is21 t r : scl sdax and sclx rise time 100 khz mode 1000 ns c b is specified to be from 10 pf to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 1 ) 300 ns is25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode ( 1 ) 100 ns is26 t hd : dat data input hold time 100 khz mode 0 ? s 400 khz mode 0 0.9 ? s 1 mhz mode ( 1 ) 00 . 3 ? s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.6 ? s is34 t hd : sto stop condition hold time 100 khz mode 4000 ns 400 khz mode 600 ns 1 mhz mode ( 1 ) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode ( 1 ) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode ( 1 ) 0.5 ? s is50 c b bus capacitive loading 400 pf note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 328 ? 2008-2014 microchip technology inc. = table 24-40: 10-bit high-spe ed adc module specifications ac characteristics standard operating conditions (see note 2 ): 3.0v and 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40 c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units conditions device supply ad01 av dd module v dd supply av dd is internally connected to v dd ; see parameter dc10 in ta b l e 2 4 - 4 ad02 av ss module v ss supply av ss is internally connected to v ss analog input ad10 v inh -v inl full-scale input span v ss v dd v ad11 v in absolute input voltage av ss a v dd v ad12 i ad operating current 8 ma ad13 leakage current 0.6 ? av inl = av ss = 0v, av dd = 3.3v, source impedance = 100 ? ad17 r in recommended impedance of analog voltage source 100 ? dc accuracy @ 1.5 msps ad20a nr resolution 10 data bits ad21a inl integral nonlinearity -0.5 -0.3/+0.5 +1.2 lsb ad22a dnl differential nonlinearity -0.9 0.6 +0.9 lsb ad23a g err gain error 13 15 22 lsb ad24a e off offset error 6 7 8 lsb ad25a monotonicity ( 1 ) guaranteed dc accuracy @ 1.7 msps ad20b nr resolution 10 data bits ad21b inl integral nonlinearity -0.5 -0.4/+1.1 +1.8 lsb ad22b dnl differential nonlinearity -1.0 1.0 +1.5 lsb ad23b g err gain error 13 15 22 lsb ad24b e off offset error 6 7 8 lsb ad25b monotonicity ( 1 ) guaranteed dc accuracy @ 2.0 msps ad20c nr resolution 10 data bits ad21c inl integral nonlinearity -0.8 -0.5/+1.8 +2.8 lsb ad22c dnl differential nonlinearity -1.0 -1.0/+1.8 +2.8 lsb ad23c g err gain error 14 16 23 lsb ad24c e off offset error 6 7 8 lsb ad25c monotonicity ( 1 ) guaranteed dynamic performance ad30 thd total harmonic distortion -73 db ad31 sinad signal to noise and distortion 58 db ad32 sfdr spurious free dynamic range -73 db ad33 f nyq input signal bandwidth 1 mhz ad34 enob effective number of bits 9.4 bits note 1: the analog-to-digital conversion result never decreases with an increase in input voltage, and has no missing codes. 2: module is functional at v bor < v dd < v ddmin , but with degraded performance. module functionality is tested but not characterized. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 329 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 24-23: analog-to-digital conversion timing per input table 24-41: 10-bit, high-speed adc module timing requirements ac characteristics standard operating conditions (see note 2 ): 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40 c ? t a ? +125c for extended param no. symbol characteristic min. typ ( 1 ) max. units conditions clock parameters ad50b t ad adc clock period 35.8 ns conversion rate ad55b t conv conversion time 14 t ad ad56b f cnv throughput rate devices with single sar 2.0 msps devices with dual sars 4.0 msps timing parameters ad63b t dpu time to stabilize analog stage from adc off to adc on 1.0 10 ? s note 1: these parameters are characterized but not tested in manufacturing. 2: module is functional at v bor < v dd < v ddmin , but with degraded performance. module functionality is tested but not characterized. t ad adc data adbufxx 98 210 old data new data conv adc clock trigger pulse t conv downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 330 ? 2008-2014 microchip technology inc. table 24-42: comparator module specifications dc characteristics standard operating conditions (see note 2 ): 3.0v to 3.6v operating temperature: -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. symbol characteristic min typ max units comments cm10 v ioff input offset voltage -58 +14/-40 66 mv cm11 v icm input common-mode voltage range ( 1 ) 0a v dd C 1.5 v cm12 v gain open loop gain (1) 90 db cm13 cmrr common-mode rejection ratio ( 1 ) 70 db cm14 t resp large signal response 21 30 49 ns v+ input step of 100 mv while v- input held at av dd /2. delay measured from analog input pin to pwm output pin. note 1: parameters are for design guidance only and are not tested in manufacturing. 2: module is functional at v bor < v dd < v ddmin , but with degraded performance. module functionality is tested but not characterized. table 24-43: dac mo dule specifications ac and dc characteristics standard operating conditions (see note 2 ): 3.0v to 3.6v operating temperature: -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. symbol characteristic min typ max units comments da01 extref external voltage reference ( 1 ) 0a v dd C 1.6 v da08 intref internal voltage reference ( 1 ) 1.25 1.32 1.41 v da02 cv res resolution 10 bits da03 inl integral nonlinearity error -7 -1 +7 lsb av dd = 3.3v, dac ref = (av dd /2)v da04 dnl differential nonlinearity error -5 -0.5 +5 lsb da05 eoff offset error 0.4 -0.8 2.6 % da06 eg gain error 0.4 -1.8 5.2 % da07 t set settling time ( 1 ) 711 1551 2100 nsec measured when range = 1 (high range), and cmref<9:0> transitions from 0x1ff to 0x300. note 1: parameters are for design guidance only and are not tested in manufacturing. 2: module is functional at v bor < v dd < v ddmin , but with degraded performance. module functionality is tested but not characterized. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 331 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 24-44: dac output buffer dc specifications dc characteristics standard operating conditions (see note 1 ): 3.0v to 3.6v operating temperature: -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. symbol characteristic min typ max units comments da10 r load resistive output load impedance 3k ? da11 c load output load capacitance 20 35 pf da12 i out output current drive strength -1740 1400 +1770 ? a sink and source da13 v range full output drive strength voltage range av ss + 250 mv av dd C 900 mv v da14 v lrange output drive voltage range at reduced current drive of 50 ? a av ss + 50 mv av dd C 500 mv v da15 i dd current consumed when module is enabled, high-power mode 369 626 948 ? a module will always consume this current even if no load is connected to the output da16 r outon output impedance when module is enabled 1200 ? note 1: module is functional at v bor < v dd < v ddmin , but with degraded performance. module functionality is tested but not characterized. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 332 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 333 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 25.0 high-temperature el ectrical characteristics this section provides an overview of dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 electrical characteristics for devices operating in an ambient temperature range of -40c to +150c. the specifications between -40c to +150c are identical to those shown in section 24.0 electrical characteristics for operation between -40c to +125c, with the exception of the parameters listed in this section. parameters in this section begin with an h, which denotes high temperature. for example, parameter dc10 in section 24.0 electrical characteristics is the industrial and extended temperature equivalent of hdc10. absolute maximum ratings for the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 high-temperature de vices are listed below. exposure to these maximum rating conditions for extended periods can affect device reliability. functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings ( 1 ) ambient temperature under bias ( 3 ) .........................................................................................................-40c to +150c storage temperature ............................................................................................................ .................. -65c to +160c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss ( 4 ) .................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd < 3.0v ( 4 ) ....................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 3.0v ( 4 ) .................................................... -0.3v to 5.6v maximum current out of v ss pin ........................................................................................................................... ..60 ma maximum current into v dd pin ( 2 ) .............................................................................................................................60 ma maximum junction temperature................................................................................................... .......................... +155c maximum current sourced/sunk by any 4x i/o pin ................................................................................. ...................4 ma maximum current sourced/sunk by any 8x i/o pin ................................................................................. ...................8 ma maximum current sourced/sunk by any 16x i/o pin ................................................................................ ................16 ma maximum current sunk by all ports combined .................................................................................... ..................180 ma maximum current sourced by all ports combined ( 2 ) ..............................................................................................180 ma note: programming of the flash memory is not allowed above +125c. note 1: stresses above those listed under absolute maximum ratings can cause permanent damage to the device. this is a stress rating only, and functional operation of the device at those or any other con ditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods can affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see tab l e 2 5- 2 ). 3: aec-q100 reliability testing for devices intended to operate at 150c is 1,000 hours. any design in which the total operating time from 125c to 150c will be greater than 1,000 hours is not warranted without prior written approval from microchip technology inc. 4: refer to the pin diagrams section for 5v tolerant pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 334 ? 2008-2014 microchip technology inc. 25.1 high-temperature dc characteristics table 25-1: operating mips vs. voltage note 1: overall functional device operation at v bormin < v dd < v ddmin is tested but not characterized. all device analog modules such as the adc, etc., will function but with degraded performance below v ddmin . refer to parameter bo10 in table 24-11 for bor values. table 25-2: thermal operating conditions table 25-3: dc temperature and voltage specifications characteristic v dd range (in volts) temperature range (in c) max mips dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 3.0v to 3.6v ( 1 ) -40c to +150c 20 rating symbol min typ max unit high-temperature devices operating junction temperature range t j -40 +155 c operating ambient temperature range t a -40 +150 c power dissipation: internal chip power dissipation: p int = v dd x (i dd - ? i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ? ({v dd - v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t j - t a )/ ? ja w dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. symbol characteristic min typ max units conditions operating voltage hdc10 supply voltage v dd 3.0 3.3 3.6 v -40c to +150c downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 335 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 25-4: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. typical ( 1 ) max units conditions power-down current (i pd ) ( 2 , 4 ) hdc60e 1000 2000 ? a +150c 3.3v base power-down current hdc61c 100 110 ? a +150c 3.3v watchdog timer current: ? i wdt ( 3 ) note 1: data in the typical column is at 3.3v, +25c unless otherwise stated. 2: i pd (sleep) current is measured as follows: cpu core is off, oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled all peripheral modules are disabled (pmdx bits are all ones) the vregs bit (rcon<8>) = 0 (i.e., core regulator is set to stand-by while the device is in sleep mode) jtag disabled 3: the ? current is the additional current consumed when the wdt module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device containing the most memory in this family. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 336 ? 2008-2014 microchip technology inc. table 25-5: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param. symbol characteristic min. typ. max. units conditions do10 v ol output low voltage i/o pins: 4x sink driver pins C ra0-ra2, rb0-rb2, rb5- rb10, rb15, rc1, rc2, rc9, rc10 0 . 4v i ol ? 3.6 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 8x sink driver pins C rc0, rc3-rc8, rc11-rc13 0 . 4v i ol ? 6 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 16x sink driver pins C ra3, ra4, rb3, rb4, rb11-rb14 0 . 4v i ol ? 12 ma, v dd = 3.3v see note 1 do20 v oh output high voltage i/o pins: 4x source driver pins C ra0-ra2, rb0-rb2, rb5- rb10, rb15, rc1, rc2, rc9, rc10 2.4 v i ol ? -4 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins C rc0, rc3-rc8, rc11-rc13 2.4 v i ol ? -8 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 16x source driver pins C ra3, ra4, rb3, rb4, rb11-rb14 2.4 v i ol ? -16 ma, v dd = 3.3v see note 1 do20a v oh 1 output high voltage i/o pins: 4x source driver pins C ra0-ra2, rb0-rb2, rb5- rb10, rb15, rc1, rc2, rc9, rc10 1.5 v i oh ? -3.9 ma, v dd = 3.3v see note 1 2.0 i oh ? -3.7 ma, v dd = 3.3v see note 1 3.0 i oh ? -2 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins C rc0, rc3-rc8, rc11-rc13 1.5 v i oh ? -7.5 ma, v dd = 3.3v see note 1 2.0 i oh ? -6.8 ma, v dd = 3.3v see note 1 3.0 i oh ? -3 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 16x source driver pins C ra3, ra4, rb3, rb4, rb11-rb14 1.5 v i oh ? -15 ma, v dd = 3.3v see note 1 2.0 i oh ? -14 ma, v dd = 3.3v see note 1 3.0 i oh ? -7 ma, v dd = 3.3v see note 1 note 1: parameters are characterized, but not tested. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 337 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 25-6: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param no. symbol characteristic ( 1 ) min typ max units conditions program flash memory hd130 e p cell endurance 10,000 e/w -40 ? c to +150 ? c ( 2 ) hd134 t retd characteristic retention 20 year 1000 e/w cycles or less and no other specifications are violated note 1: these parameters are assured by design, but are not characterized or tested in manufacturing. 2: programming of the flash memory is not allowed above +125c. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 338 ? 2008-2014 microchip technology inc. 25.2 ac characteristics and timing parameters the information contained in this section defines dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 ac characteristics and timing parameters for high- temperature devices. however, all ac timing specifications in this section are the same as those in section 24.2 ac characteristics and timing parameters , with the exception of the parameters listed in this section. parameters in this section begin with an h, which denotes high temperature. for example, parameter os53 in section 24.2 ac characteristics and timing parameters is the industrial and extended temperature equivalent of hos53. table 25-7: temperature and volt age specifications C ac figure 25-1: load conditions for device timing specifications table 25-8: pll clock timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature operating voltage v dd range as described in table 25-1 . ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param no. symbol characteristic min typ max units conditions hos53 d clk clko stability (jitter) ( 1 ) -5 0.5 5 % measured over 100 ms period note 1: these parameters are characterized, but are not tested in manufacturing. v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 C for all pins except osc2 load condition 2 C for osc2 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 339 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 25-9: spix master mode (cke = 0 ) timing requirements table 25-10: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param no. symbol characteristic ( 1 ) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 1 02 5n s hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 28 ns hsp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 35 ns note 1: these parameters are characterized but not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param no. symbol characteristic ( 1 ) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 1 02 5n s hsp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 35 ns hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 28 ns hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 35 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 340 ? 2008-2014 microchip technology inc. table 25-11: spix modul e slave mode (cke = 0 ) timing requirements table 25-12: spix modul e slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param no. symbol characteristic ( 1 ) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 3 5n s hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 25 ns hsp41 tsch2dil, tsc l2 di l hold time of sdix data input to sckx edge 25 ns hsp51 tssh2doz ssx ? to sdox output high-impedance 15 55 ns see note 2 note 1: these parameters are characterized but not tested in manufacturing. 2: assumes 50 pf load on all spix pins. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature param no. symbol characteristic ( 1 ) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 3 5n s hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 25 ns hsp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 25 ns hsp51 tssh2doz ssx ? to sdo x output high-impedance 15 55 ns see note 2 hsp60 tssl2dov sdox data output valid after ssx edge 5 5n s note 1: these parameters are characterized but not tested in manufacturing. 2: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 341 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 26.0 50 mips electrical characteristics this section provides an overview of dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 electrical characteristics for devices operating at 50 mips. the specifications for 50 mips are identical to those shown in section 24.0 electrical characteristics , with the exception of the parameters listed in this section. parameters in this section begin with the letter m, which denotes 50 mips operation. for example, parameter dc29a in section 24.0 electrical characteristics , is the up to 40 mips operation equivalent of mdc29a. absolute maximum ratings for the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 50 mips devices are listed below. exposure to these maximum rating conditions for extended periods can affect device reliability. functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings ( 1 ) ambient temperature under bias................................................................................................. ............. .-40c to +85c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss ( 3 ) ................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss , when vdd ? 3.0v ( 3 ) ................................................. -0.3v to +5.6v voltage on any 5v tolerant pin with respect to vss, when v dd < 3.0v ( 3 ) ........................................ -0.3v to (v dd + 0.3v) maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ( 2 ) ...........................................................................................................................250 ma maximum current sourced/sunk by any 4x i/o pin ................................................................................. .................15 ma maximum current sourced/sunk by any 8x i/o pin ................................................................................. .................25 ma maximum current sourced/sunk by any 16x i/o pin ................................................................................ ................45 ma maximum current sunk by all ports .......................................................................................................................200 ma maximum current sourced by all ports ( 2 ) ...............................................................................................................200 ma note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at those or any other con ditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see tab l e 2 4- 2 ). 3: see the pin diagrams section for 5v tolerant pins. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 342 ? 2008-2014 microchip technology inc. 26.1 dc characteristics table 26-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) max mips dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 3.0-3.6v ( 1 ) -40c to +85c 50 note 1: overall functional device operation at v bormin < v dd < v ddmin is tested but not characterized. all device analog modules, such as the adc, etc., will function but with degraded performance below v ddmin . refer to parameter bo10 in table 24-11 for bor values. table 26-2: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical max units conditions operating current (i dd ) ( 1 ) mdc29d 105 125 ma -40c 3.3v 50 mips mdc29a 105 125 ma +25c mdc29b 105 125 ma +85c note 1: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: oscillator is configured in ec mode with pll, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) cpu executing while(1) statement jtag is disabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 343 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 table 26-3: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical max units conditions idle current (i idle ): core off, clock on base current ( 1 ) mdc45d 64 105 ma -40c 3.3v 50 mips mdc45a 64 105 ma +25c mdc45b 64 105 ma +85c note 1: base idle current (i idle ) is measured as follows: cpu core is off, oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) the nvmsidl bit (nvmcon<12>) = 1 (i.e., flash regulator is set to standby while the device is in idle mode) jtag is disabled downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 344 ? 2008-2014 microchip technology inc. table 26-4: dc characteristics: doze current (i doze ) ( 1 ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical max doze ratio units conditions mdc74a 80 105 1:2 ma -40c 3.3v 50 mips mdc74f 65 105 1:64 ma mdc74g 65 105 1:128 ma mdc75a 81 105 1:2 ma +25c 3.3v 50 mips mdc75f 65 105 1:64 ma mdc75g 65 105 1:128 ma mdc76a 81 105 1:2 ma +85c 3.3v 50 mips mdc76f 65 105 1:64 ma mdc76g 65 105 1:128 ma note 1: i doze is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i doze measurements are as follows: oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating; however, every peripheral is being clocked (all pmdx bits are zeroed) cpu executing while(1) statement jtag is disabled downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 345 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 26.2 ac characteristics and timing parameters this section defines the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ac characteristics and timing parameters for 50 mips devices. table 26-5: external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symb characteristic min typ ( 1 ) max units conditions mos10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc 50 mhz ec oscillator crystal frequency 3.5 10 1050 mhzmhz xths mos20 t osc t osc = 1/f osc 10 dc ns mos25 t cy instruction cycle time ( 2 ) 20 dc ns note 1: data in typ column is at 3.3v, +25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type, under standard operating condition s, with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at min. values with an external clock applied to the osc1/clki pin. when an external clock input is used, the max. cycle time limit is dc (no clock) for all devices. table 26-6: simple ocx/pwmx mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic ( 1 ) min typ max units conditions moc15 t fd fault input to pwmx i/o change t cy + 10 ns moc20 t flt fault input pulse width t cy + 10 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 346 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 347 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 27.0 dc and ac device characteristics graphs figure 27-1: v oh C 4x driver pins figure 27-2: v oh C 8x driver pins figure 27-3: v oh C 16x driver pins note: the graphs provided following this note are a statistical summary ba sed on a limited number of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs, the dat a presented may be out side the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. -0.030 -0.025 -0.020 -0.015 -0.010 ioh (a) -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh (a) voh (v) 3v 3.3v 3.6v absolute maximum -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 ioh (a) -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 1.00 2.00 3.00 4.00 ioh (a) voh (v) 3v 3.3v 3.6v absolute maximum -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 ioh (a) -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 -0.010 0.000 0.00 1.00 2.00 3.00 4.00 ioh (a) voh (v) 3.3v 3.6v absolute maximum 3v downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 348 ? 2008-2014 microchip technology inc. figure 27-4: v ol C 4x driver pins figure 27-5: v ol C 8x driver pins figure 27-6: v ol C 16x driver pins 0.010 0.015 0.020 0.025 0.030 0.035 0.040 iol (a) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v absolute maximum 0.020 0.030 0.040 0.050 0.060 iol (a) 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v absolute maximum 0.040 0.060 0.080 0.100 0.120 iol (a) 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v absolute maximum downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 349 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 figure 27-7: typical i pd current @ v dd = 3.3v figure 27-8: typical i dd current @ v dd = 3.3v figure 27-9: typical i doze current @ v dd = 3.3v figure 27-10: typical i idle current @ v dd = 3.3v 420 620 820 1020 1220 i pd current (a) 20 220 420 620 820 1020 1220 - 4 02 56 58 51 2 51 5 0 i pd current (a) temperature (celsius) 70 80 90 100 110 120 average (ma) 40 50 60 70 80 90 100 110 120 10 20 30 40 50 average (ma) mips 48 58 68 78 88 98 108 118 o ze current (ma) 18 28 38 48 1:1 1:2 1:64 1:128 i d o doze ratio 50 mips 40 mips 50 55 60 65 70 average (ma) 40 45 50 55 60 65 70 10 20 30 40 50 average (ma) mips downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 350 ? 2008-2014 microchip technology inc. figure 27-11: typical frc frequency @ v dd = 3.3v figure 27-12: typical lprc frequency @ v dd = 3.3v figure 27-13: typical intref @ v dd = 3.3v 71 7.15 7.2 7.25 7.3 7.35 7.4 7.45 f rc frequency (mhz) 7 7.05 7.1 7.15 7.2 7.25 7.3 7.35 7.4 7.45 -40 25 85 125 150 frc frequency (mhz) temperature (celsius ) 22 24 26 28 30 32 34 l prc frequency (khz) 18 20 22 24 26 28 30 32 34 -40 25 85 125 150 lprc frequency (khz) temperature (celsius ) 1.31 1.32 1.33 1.34 1.35 1.36 intref (v) 1.29 1.3 1.31 1.32 1.33 1.34 1.35 1.36 -40 25 85 125 150 intref (v) temperature (celsius) downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 351 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 28.0 packaging information 28.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : if the full microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic33fj06gs 0830235 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic33fj06gs 0830235 202-e/sp 202-e/so 3 e 3 e 18-lead soic (.300) xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example dspic33fj06 0830235 gs101-i/so 3 e 28-lead qfn-s xxxxxxxx xxxxxxxx yywwnnn example 33fj06gs 202emm 0830235 3 e downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 352 ? 2008-2014 microchip technology inc. 28.1 package marking information (continued) 28-lead uqfn xxxxxxxx xxxxxxxx yywwnnn example 33fj06gs 202emx 0830235 xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn dspic33fj16 example gs504-e/ml 0830235 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example dspic33fj 16gs504 0830235 -e/pt 3 e 3 e 3 e xxxxxxxxxx 44-lead vtla (tla) xxxxxxxxxx xxxxxxxxxx yywwnnn dspic33fj example -e/tl 0830235 16gs504 3 e downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 353 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 28.2 package details note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 354 ? 2008-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 355 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 356 ? 2008-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 357 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 358 ? 2008-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 359 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ! 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'! 9'&! 7 7: ; 7"') %9 #! 7 9 # & <1, : 8 & = = ## 4 4!! & # %% = 3 &9& 9 ? 3 & & 9 .3 3 & c - c c : >#& . 1, : 9& 1, ## 4 >#& . 1, ## 4 9& 1, 9 # 4!! = 9 #>#& ) - - # %& c c -c # %&1 && ' c c -c a e e1 d d1 e b note 1 note 2 n 123 c a1 l a2 l1 * ,?1 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 369 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 370 ? 2008-2014 microchip technology inc. b a 0.20 c 0.20 c c seating plane 2x top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 1 2 0.10 c a b 0.10 c a 0.10 c 0.08 c a1 microchip technology drawing c04-157d sheet 1 of 2 44-terminal very thin leadless array package (tl) ? 6x6x0.9 mm body d e 10 11 22 2332 33 n 12 n (datum b) (datum a) note 1 d2 e2 with exposed pad [vtla] (nd-1) x e (ne-1) x e 44x k a detail a 2x downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 371 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-157d sheet 2 of 2 0.30 0.20 0.25 terminal length l terminal-to-exposed pad ref: reference dimension, usually without tolerance, for information purposes only. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. 1. pin 1 visual index feature may vary, but must be located within the hatched area. notes: 2. package is saw singulated. k- 0.20 - overall height overall length exposed pad width number of terminals terminal width exposed pad length overall width standoff pitch e2 d2 b d e a1 4.70 4.40 4.55 6.00 bsc 0.25 4.55 4.400.20 4.700.30 - 6.00 bsc 0.025 0.075 dimension limits e a n units max min nom 0.50 bsc 0.90 44 0.80 1.00 millimeters number of terminals per side nd 12 number of terminals per side ne 10 e e/2 44x b 0.10 c a b 0.05 c 44x l detail a 44-terminal very thin leadless array package (tl) ? 6x6x0.9 mm body with exposed pad [vtla] (datum a or b) downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 372 ? 2008-2014 microchip technology inc. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 373 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 appendix a: revision history revision a (january 2008) this is the initial revision of this document. revision b (june 2008) this revision includes minor typographical and formatting changes throughout the data sheet text. in addition, redundant information was removed that is now available in the respective chapters of the dspic33f/pic24h family reference manual , which can be obtained from the microchip web site ( www.microchip.com ). the major changes are referenced by their respective section in the following table. table a-1: major section updates section name update description high-performance, 16-bit digital signal controllers moved location of note 1 (rpn pin) references (see pin diagrams ). section 3.0 memory organization updated cpu core register map sfr reset value for corcon (see ta bl e 3 - 1 ). removed interrupt controller register map sfr ipc29 and updated reset values for ipc0, ipc1, ipc14, ipc16, ipc23, ipc24, ipc27, and ipc28 (see ta bl e 3 - 5 ). removed interrupt controller register map sfr ipc24 and ipc29 and updated reset values for ipc0, ipc1, ipc2, ipc14, ipc16, ipc23, ipc27, and ipc28 (see table 3-6). removed interrupt controller register map sfr ipc24 and updated reset values for ipc1, ipc2, ipc4, ipc14, ipc16, ipc23, ipc24, ipc27, and ipc28 (see table 3-7). updated interrupt controller register map sfr reset values for ipc1, ipc14, ipc16, ipc23, ipc24, ipc27, and ipc28 (see table 3-8). updated interrupt controller register map sfr reset values for ipc1, ipc14, ipc16, ipc23, ipc24, ipc25, ipc26, ipc27, ipc28, and ipc29 (see ta bl e 3 - 9 ). updated interrupt controller register map sfr reset values for ipc1, ipc4, ipc14, ipc16, ipc23, ipc24, ipc25, ipc26, ipc27, ipc28, and ipc29 (see table 3-10). added sfr definitions for rpor16 and rpor17 (see table 3-34, table 3-35, and table 3-36). updated bit definitions for porta, portb, and portc sfrs (odca, odcb, and odcc) (see table 3-37, table 3-38, table 3-39, and table 3-40). updated bit definitions and reset value for system control register map sfr clkdiv (see table 3-41). added device-specific information to title of pmd register map (see table 3-47). added device-specific pmd register maps (see table 3-46, table 3-45, and table 3-43). downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 374 ? 2008-2014 microchip technology inc. section 7.0 oscillator configuration removed the first sentence of the third clock source item (external clock) in section 7.1.1 system clock sources updated the default bit values for doze and frcdiv in the clock divisor register (see register 7-2). section 8.0 power-saving features added the following six registers: pmd1: peripheral module disable control register 1 pmd2: peripheral module disable control register 2 pmd3: peripheral module disable control register 3 pmd4: peripheral module disable control register 4 pmd6: peripheral module disable control register 6 pmd7: peripheral module disable control register 7 section 9.0 i/o ports added paragraph and table 9-1 to section 9.1.1 open-drain configuration , which provides details on i/o pins and their functionality. removed 9.1.2 5v tolerance. updated mux range and removed virtual pin details in figure 9-2. updated pwm input name descriptions in table 9-1. added section 9.4.2.3 virtual pins . updated bit values in all peripheral pin select input registers (see register 9-1 through register 9-14). updated bit name information for peripheral pin select output registers rpor16 and rpor17 (see register 9-30 and register 9-31). added the following two registers: rpor16: peripheral pin select output register 16 rpor17: peripheral pin select output register 17 removed the following sections: 9.4.2 available peripherals 9.4.3.2 virtual input pins 9.4.3.4 peripheral mapping 9.4.5 considerations for peripheral pin selection (and all subsections) section 14.0 high-speed pwm added note 1 (remappable pin reference) to figure 14-1. added note 2 (duty cycle resolution) to pwm master duty cycle register (register 14-5), pwm generator duty cycle register (register 14-7), and pwm secondary duty cycle register (register 14-8). added note 2 and note 3 and updated bit information for clsrc and fltsrc in the pwm fault current-limit control register (register 14-15). section 15.0 serial peripheral interface (spi) removed the following sections, which are now available in the related section of the dspic33f/pic24h family reference manual: 15.1 interrupts 15.2 receive operations 15.3 transmit operations 15.4 spi setup (retained figure 15-1: spi module block diagram) table a-1: major section updates (continued) section name update description downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 375 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 section 16.0 inter-integrated circuit (i 2 c?) removed the following sections, which are now available in the related section of the dspic33f/pic24h family reference manual: 16.3 i 2 c interrupts 16.4 baud rate generator (retained figure 16-1: i 2 c block diagram) 16.5 i 2 c module addresses 16.6 slave address masking 16.7 ipmi support 16.8 general call address support 16.9 automatic clock stretch 16.10 software controlled clock stretching (stren = 1 ) 16.11 slope control 16.12 clock arbitration 16.13 multi-master communication, bus collision, and bus arbitration section 17.0 universal asynchronous receiver transmitter (uart) removed the following sections, which are now available in the related section of the dspic33f/pic24h family reference manual: 17.1 uart baud rate generator 17.2 transmitting in 8-bit data mode 17.3 transmitting in 9-bit data mode 17.4 break and sync transmit sequence 17.5 receiving in 8-bit or 9-bit data mode 17.6 flow control using uxcts and uxrts pins 17.7 infrared support removed irda references and note 1, and updated the bit and bit value descriptions for utxinv (uxsta<14>) in the uartx status and control register (see register 17-2). section 18.0 high-speed 10-bit analog-to-digital converter (adc) updated bit value information for analog-to-digital control register (see register 18-1). updated trgsrc6 bit value for timer1 period match in the analog-to- digital convert pair control register 3 (see register 18-8). table a-1: major section updates (continued) section name update description downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 376 ? 2008-2014 microchip technology inc. section 23.0 electrical characteristics updated typ values for thermal packaging characteristics (table 23-3). removed typ value for dc temperature and voltage specifications parameter dc12 (table 23-4). updated all typ values and conditions for dc characteristics: operating current (i dd ), updated last sentence in note 2 (table 23-5). updated all typ values for dc characteristics: idle current (i idle ) (see table 23-6). updated all typ values for dc characteristics: power down current (i pd ) (see table 23-7). updated all typ values for dc characteristics: doze current (i doze ) (see table 23-8). added note 4 (reference to new table containing digital-only and analog pin information, as well as current sink/source capabilities) in the i/o pin input specifications (table 23-9). updated max value for bor electrical characteristics parameter bo10 (see table 23-11). swapped min and typ values for program memory parameters d136 and d137 (table 23-12). updated typ values for internal rc accuracy parameter f20 and added extended temperature range to table heading (see table 23-19). removed all values for reset, watchdog timer, oscillator start-up timer, and power-up timer parameter sy20 and updated conditions, which now refers to section 20.4 watchdog timer (wdt) and lprc parameter f21a (see table 23-22). added specifications to high-speed pwm module timing requirements for tap delay (table 23-29). updated min and max values for 10-bit high-speed analog-to-digital module parameters ad01 and ad11 (see table 23-36). updated max value and unit of measure for dac ac specification (see table 23-40). table a-1: major section updates (continued) section name update description downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 377 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 revision c and d (march 2009) this revision includes minor typographical and formatting changes throughout the data sheet text. global changes include: changed all instances of osci to osc1 and osco to osc2 changed all instances of pgcx/emucx and pgdx/emudx (where x = 1, 2, or 3) to pgecx and pgedx changed all instances of v ddcore and v ddcore / v cap to v cap /v ddcore other major changes are referenced by their respective section in the following table. table a-2: major section updates section name update description high-performance, 16-bit digital signal controllers added application examples to list of features updated all pin diagrams to denote the pin voltage tolerance (see pin diagrams ). added note 2 to the 28-pin qfn-s and 44-pin qfn pin diagrams, which references pin connections to v ss . section 1.0 device overview added acmp1-acmp4 pin names and peripheral pin select capability column to pinout i/o descriptions (see table 1-1). section 2.0 guidelines for getting started with 16-bit digital signal controllers added new section to the data sheet that provides guidelines on getting started with 16-bit digital signal controllers. section 3.0 cpu updated cpu core block diagram with a connection from the dsp engine to the y data bus (see figure 3-1). vertically extended the x and y data bus lines in the dsp engine block diagram (see figure 3-3). section 4.0 memory organization updated reset value for adcon in table 4-25. removed reference to dspic33fj06gs102 devices in the pmd register map and updated bit definitions for pmd1 and pmd6, and removed pmd7 (see table 4-43). added a new pmd register map, which references dspic33fj06gs102 devices (see table 4-44). updated ram stack address and splim values in the third paragraph of section 4.2.6 software stack removed section 4.2.7 data ram protection feature . section 5.0 flash program memory updated section 5.3 programming operations with programming time formula. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 378 ? 2008-2014 microchip technology inc. section 8.0 oscillator configuration added note 2 to the oscillator system diagram (see figure 8-1). added a paragraph regarding frc accuracy at the end of section 8.1.1 system clock sources . added note 1 and note 2 to the oscon register (see register ). added note 1 to the osctun register (see register 8-4). added note 3 to section 8.4.2 oscillator switching sequence . section 10.0 i/o ports removed table 9-1 and added reference to pin diagrams for i/o pin availability and functionality. added paragraph on adpcfg register default values to section 10.3 configuring analog port pins . added note box regarding pps functionality with input mapping to section 10.6.2.1 input mapping . section 15.0 high-speed pwm updated note 2 in the ptcon register (see register 15-1). added note 4 to the pwmconx register (see register 15-6). updated notes for the phasex and sphasex registers (see register 15-9 and register 15-10, respectively). section 16.0 serial peripheral interface (spi) added note 2 and note 3 to the spixcon1 register (see register 16-2). section 18.0 universal asynchronous receiver transmitter (uart) updated the notes in the uxmode register (see register 18-1). updated the utxinv bit settings in the uxsta register and added note 1 (see register 18-2). section 19.0 high-speed 10-bit analog-to-digital converter (adc) updated the slowclk and adcs<2:0> bit settings and updated note 1in the adcon register (see register 19-1). removed all notes in the adpcfg register and replaced them with a single note (see register 19-4). updated the swtrgx bit settings in the adcpcx registers (see register 19-5, register 19-6, register 19-7, and register 19-8). table a-2: major section updates (continued) section name update description downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 379 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 section 24.0 electrical characteristics updated typical values for thermal packaging characteristics (see table 24-3). updated min and max values for parameter dc12 (ram data retention voltage) and added note 4 (see table 24-4). updated characteristics for i/o pin input specifications (see table 24-9). added i source to i/o pin output specifications (see table 24-10). updated program memory values for parameters 136, 137, and 138 (renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and 138b, and added note 2 (see table 24-12). added parameter os42 (g m ) to the external clock timing requirements (see table 24-16). updated conditions for symbol t pdly (tap delay) and added symbol a clk (pwm input clock) to the high-speed pwm module timing requirements (see table 24-29). updated parameters ad01 and ad02 in the 10-bit high-speed analog-to- digital module specifications (see table 24-36). updated parameters ad50b, ad55b, and ad56b, and removed parameters ad57b and ad60b from the 10-bit high-speed analog-to-digital module timing requirements (see table 24-37). table a-2: major section updates (continued) section name update description downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 380 ? 2008-2014 microchip technology inc. revision e (december 2009) the revision includes the following global update: added note 2 to the shaded table that appears at the beginning of each chapter. this new note provides information regarding the availability of registers and their associated bits this revision also includes minor typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. table a-3: major section updates section name update description 16-bit microcontrollers and digital signal controllers (up to 16-kbyte flash and up to 2-kbyte sram) with high-speed pwm, adc and comparators changed cn6 to cn5 on pin 16 of dspic33fj16gs502 28-pin spdip, soic pin diagram. section 2.0 guidelines for getting started with 16-bit digital signal controllers removed the 10 ohm resistor from figure 2-1. section 4.0 memory organization renamed bit 13 of the refocon sfr in the system control register map from rosidl to rosslp and changed the all resets value from 0000 to 2300 for the aclkcon sfr (see 4-41). section 8.0 oscillator configuration updated the default reset values from r/w-0 to r/w-1 for the selaclk and apstsclr<2:0> bits in the aclk con register (see register 8-5). renamed the rosidl bit to rosslp in the refocon register (see register 8-6). section 9.0 power-saving features updated the last paragraph of section 9.2.2 idle mode to clarify when instruction execution begins. added note 1 to the pmd1 register (see register 9-1). section 10.0 i/o ports changed the reference to digital-only pins to 5v tolerant pins in the second paragraph of section 10.2 open-drain configuration . section 15.0 high-speed pwm updated the smallest pulse width value from 0x0008 to 0x0009 in note 1 of the shaded note that follows the mdc register (see register 15-5). updated the smallest pulse width value from 0x0008 to 0x0009 and the maximum pulse width value from 0x0ffef to 0x0008 in note 2 of the shaded note that follows the pdcx and sdcx registers (see register 15-7 and register 15-8). added note 2 and updated the fltdat<1:0> and cldat<1:0> bits, changing the word data to state in the ioconx register (see register 15-14). section 18.0 universal asynchronous receiver transmitter (uart) updated the two baud rate range features to: 10 mbps to 38 bps at 40 mips. downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 381 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 section 19.0 high-speed 10-bit analog-to-digital converter (adc) updated note 1 in the adcpc0 register (see register 19-5). updated note 3 in the adcpc1 register (see register 19-6). updated note 2 in the adcpc2 and adcpc3 registers (see register 19- 7 and register 19-8). section 21.0 special features updated the second paragraph and removed the fourth paragraph in section 21.1 configuration bits . updated the device configuration register map (see table 21-1). section 24.0 electrical characteristics updated the absolute maximum ratings for high temperature and added note 4. updated idle current (i idle ) typical values in table 24-6. updated the typ and max values for parameter di50 in the i/o pin input specifications table (see table 24-9). updated the typ and max values for parameters do10 and do27 and the min and typ values for parameter do20 in the i/o pin output specifications (see table 24-10). added parameter numbers to the auxiliary pll clock timing specifications (see table 24-18). added parameters numbers and updated the internal rc accuracy min, typ, and max values (see table 24-19 and table 24-20). added parameter numbers, note 2, updated the min and typ parameter values for mp31 and mp32, and removed the conditions for mp10 and mp11 in the high-speed pwm module timing requirements (see table 24-29). updated the spix module slave mode (cke = 1 ) timing characteristics (see table 24-14). added parameter im51 to the i2cx bus data timing requirements (master mode) (see table 24-34). updated the max value for parameter ad33 in the 10-bit high-speed analog-to-digital module specifications (see table 24-36). updated the titles and added parameter numbers to the comparator and dac module specifications (see table 24-38 and table 24-39) and the dac output buffer specifications (see table 24-40). table a-3: major section updates (continued) section name update description downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 382 ? 2008-2014 microchip technology inc. revision f (january 2012) all occurrences of v ddcore have been removed throughout the document. this revision also includes minor typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. table a-4: major section updates section name update description 16-bit digital signal controllers (up to 16-kbyte flash and up to 2-kbyte sram) with high-speed pwm, adc and comparators added the vtla package to the dspic33fj16gs404 and dspic33fj16gs504 devices (see table 1: dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 controller families ). added the referenced sources section. the following updates were made to the pin diagrams section: added 5v tolerant pin shading to pins 24-26 in the 28-pin spdip, soic package for the dspic33fj16gs402 updated pin 31 of the 44-pin qfn package for the dspic33fj16gs404 added vtla pin diagrams for the dspic33fj16gs404 and dspic33fj16gs504 devices section 1.0 device overview removed the precision band gap reference from the device block diagram (see figure 1-1 ). updated the pinout i/o descriptions for av dd , and av ss (see tab l e 1 - 1 ). section 2.0 guidelines for getting started with 16-bit digital signal controllers updated the minimum recommended connection (see figure 2-1 ). section 8.0 oscillator configuration updated the oscillator system diagram (see figure 8-1 ). added auxiliary clock configuration restrictions in section 8.2 auxiliary clock generation . updated or added notes regarding register reset on a por (see register 8-1 through register 8-5 ). section 19.0 high-speed 10-bit analog-to-digital converter (adc) added note 2 to adcon: analog-to-digital control register (see register 19-1 ). removed all notes from adstat: analog-to-digital status register (see register 19-2 ). section 20.0 high-speed analog comparator updated the comparator module block diagram (see figure 20-1 ). section 21.0 special features add a new paragraph at the beginning of section 21.1 configuration bits . added the rtsp effect column to the dspic33f configuration bits description table (see table 21-2 ). updated the connections for the on-chip voltage regulator diagram (see figure 21-1 ). updated the first paragraph of section 21.7 in-circuit debugger . downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 383 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 section 24.0 electrical characteristics updated the absolute maximum ratings. updated the operating mips vs. voltage (see ta b l e 2 4 - 1 ). updated parameter dc10 and note 4, and removed parameter dc18 from the dc temperature and voltage specifications (see table 24-4 ). updated note 2 in the i dd operating current specification (see ta b l e 2 4 - 5 ). updated all typical values and note 2 in the i idle operating current specification (see table 24-6 ). updated typical values for parameters dc60d, dc60a, dc60b, and dc60c, and note 2 in the i pd operating current specification (see table 24-7 ). added all typical values and note 2 in the i doze operating current specification (see table 24-8 ). updated parameters di19 and di50, added parameters di128, di129, di60a, di60b, and di60c, and removed parameter di57 in the i/o pin input specifications (see tab l e 2 4- 9 ). revised all i/o pinout output specifications (see table 24-10 ). added notes 2 and 3 to the bor electrical characteristics (see table 24- 11 ). added note 1 to internal voltage regulator specifications (see table 24-13 ). updated the external clock timing diagram (see figure 24-2 ). added note 2 to the pll clock timing specifications (see tab l e 2 4- 1 7 ). removed note 2 from the internal frc accuracy (see table 24-19 ). updated parameters do31 and do32 in the i/o timing requirements (see table 24-21 ). updated the external clock timing requirements for timer1, timer2, and timer3 (see table 24-23 , table 24-24 , and table 24-25 , respectively). updated parameters oc15 and oc20 in the simple oc/pwm mode timing requirements (see table 24-28 ). revised all spix module timing characteristics diagrams and all timing requirements (see figure 24-11 through figure 24-18 and table 24-30 through table 24-37 , respectively). added note 2 to the 10-bit high-speed adc module specifications (see table 24-40 ). added note 2 to the 10-bit high-speed adc module timing requirements (see table 24-41 ). added note 2 to the comparator module specifications (see table 24-42 ). added parameter da08 and note 2 in the dac module specifications (see table 24-43 ). updated parameter da16 and note 2 in the dac output buffer dc specifications (see table 24-44 ). table a-4: major section updates (continued) section name update description downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 384 ? 2008-2014 microchip technology inc. section 26.0 50 mips electrical characteristics added new chapter in support of 50 mips devices. section 27.0 dc and ac device characteristics graphs added new chapter. section 28.0 packaging information added 44-pin vtla package marking information and diagrams (see section 28.1 package marking information and section 28.2 package details , respectively). product identification system added the tl package definition. table a-4: major section updates (continued) section name update description downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 385 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 revision g (may 2014) the values for the tun<5:0> bits in register 8-4 (osctun) have changed. the dc characteristics idle current values in section 24.0 electrical characteristics have been updated. the timer specifications in section 26.0 50 mips electrical characteristics have been removed. all diagrams in section 28.0 packaging information have been updated. minor text edits have been applied throughout the document. downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 386 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 387 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 index a ac characteristics ............................................ 300, 338, 345 internal frc accuracy.............................................. 303 internal lprc accuracy............................................ 303 load conditions ............................................... . 300, 338 adc control registers ...................................................... 24 6 functionality.............................................................. 239 arithmetic logic unit (alu)................................................. 38 assembler mpasm assembler................................................... 284 auxiliary clock generation............................................ .... 138 b barrel shifter ....................................................................... 42 bit-reversed addressing .................................................... 76 example ...................................................................... 77 implementation ........................................................... 76 sequence table (16-entry)......................................... 77 block diagrams 16-bit timer1 module.......................................... ...... 183 connections for on-chip voltage regulator............. 270 dsp engine ................................................................ 39 dspic33f06gs101 devices with 1 sar .................. 240 dspic33f06gs102 devices with 1 sar .................. 241 dspic33f06gs202 devices with 1 sar .................. 242 dspic33f16gs402/404 devices with 1 sar ........... 243 dspic33f16gs502 devices with 2 sars ................ 244 dspic33f16gs504 devices with 2 sars ................ 245 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ................................... 18 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 cpu core.................. 32 high-speed analog comparator............................... 263 i2cx module .............................................. ............... 226 input capture x ............................................. ............ 191 multiplexing of remappable output for rpn............. 159 oscillator system ...................................................... 135 output compare x module........................................ 193 partitioned output pair, complementary pwm mode ....................................................... 200 pll............................................................................ 137 remappable mux input for u1rx............................ 157 reset system.............................................................. 89 shared port structure ............................................... 155 simplified conceptual high-speed pwm ................. 199 spix module............................................. ................. 219 timer2/3 (32-bit) ....................................................... 187 type b timer ............................................................ 185 type c timer ............................................................ 185 uart1 ...................................................................... 233 watchdog timer (wdt) ......................................... ... 271 brown-out reset (bor) ...................................... 94, 267, 270 c c compilers mplab xc compilers............................................... 284 clock switching................................................................. 146 enabling .................................................................... 146 sequence................................................. ................. 146 code examples erasing a program memory page .............................. 87 initiating a programming sequence ........................... 88 loading write buffers .......................................... ....... 88 port write/read ........................................................ 156 pwrsav instruction syntax .................................... 147 code protection ........................................................ 267, 273 codeguard security ......................................................... 2 67 configuration bits ....................................................... ...... 267 description................................................................ 268 configuration register map ............................... ............... 267 configuring analog port pins............................................ 156 cpu control registers........................................................ 34 cpu clocking system ...................................................... 136 pll configuration..................................................... 137 selection................................................................... 1 36 sources .................................................................... 136 customer change notification service............................. 392 customer notification service .......................................... 392 customer support............................................................. 392 d dac .................................................................................. 264 output range .............................................. ............. 264 data accumulators and adder/subtracter .......................... 40 data space write saturation ...................................... 42 overflow and saturation ......................................... .... 40 round logic ............................................................... 41 write back .................................................................. 41 data address space........................................................... 45 alignment.................................................................... 45 memory map for dspic33fj06gs101/102 devices with 256 bytes of ram ....................................... 46 memory map for dspic33fj06gs202 device with 1-kbyte ram............................................... 47 memory map for dspic33fj16gs402/404/502/504 devices with 2-kbyte ram ................................. 48 near data space ........................................................ 45 software stack ........................................................... 73 width .......................................................................... 45 data addressing overview..................................................................... 31 dc and ac characteristics graphs and tables ............................................... .... 347 dc characteristics.................................................... 288, 3 42 doze current (i doze )........................................ 294, 344 high temperature..................................................... 334 i/o pin input specifications ................................... ... 295 i/o pin output specifications............................ 297, 336 idle current (i idle ) ............................................ 292, 343 operating current (i dd ) .................................... 290, 342 operating mips vs. voltage ..................... 288, 334, 342 power-down current (i pd )................................ 293, 335 program memory.............................................. 299, 337 temperature and voltage......................................... 334 temperature and voltage specifications.................. 289 thermal operating conditions.................................. 334 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 388 ? 2008-2014 microchip technology inc. demo/development boards, evaluation and starter kits ................................................................ 286 development support ............................................... ........ 283 third-party tools ...................................................... 286 doze mode........................................................................ 148 dsp engine......................................................................... 38 multiplier...................................................................... 40 e electrical characteristics................................................... 287 50 mips .................................................................... 341 ac ............................................................................. 338 ac characteristics and timing parameters.................................... 300, 345 bor .......................................................................... 298 equations device operating frequency .................................... 136 f osc calculation....................................................... 137 maximum row write time .......................................... 84 minimum row write time ........................................... 84 programming time ..................................................... 84 xt with pll mode example...................................... 137 errata .................................................................................. 14 external reset (extr)........................................................ 95 f fail-safe clock monitor (fscm) ....................................... 14 6 flash program memory....................................................... 83 control registers ........................................................ 84 operations .................................................................. 84 programming algorithm .............................................. 87 rtsp operation.......................................................... 84 table instructions........................................................ 83 flexible configuration ....................................................... 267 g guidelines for getting started with 16-bit dscs................. 21 h high-speed 10-bit a nalog-to-digital converter (adc) ....................................................... 239 high-speed analog comparator ....................................... 263 digital logic .............................................................. 264 input range ............................................... ............... 264 interaction with i/o buffers........................................ 264 high-speed pwm ............................................................. 197 control registers ...................................................... 200 high-temperature electr ical characteristics..................... 333 i i/o ports ............................................................................ 155 parallel i/o (pio)....................................................... 155 write/read timing .......................................... .......... 156 i 2 c control registers ...................................................... 227 operating modes ...................................................... 225 in-circuit debugger ........................................... ................ 272 in-circuit emulation........................................................... 267 in-circuit serial programming (icsp) ....................... 267, 272 input capture .............................................. ...................... 191 control register ........................................................ 192 input change notification....................................... ........... 156 instruction addressing modes ........................................... . 73 file register instructions ............................................ 73 fundamental modes supported ................................. 74 mac instructions ........................................................ 74 mcu instructions ........................................................ 73 move and accumulator instructions............................ 74 other instructions ....................................................... 74 instruction set overview................................................................... 278 summary .................................................................. 275 instruction-based power-saving modes........................... 147 idle .......................................................................... .. 148 sleep ........................................................................ 147 interfacing program and data memory spaces.................. 78 internal rc oscillator use with wdt........................................................... 271 internet address ............................................................... 392 interrupts alternate interrupt vector table (aivt) ...................... 97 control and status registers.................................... 100 iecx.................................................................. 100 ifsx .................................................................. 100 intcon1.......................................................... 100 intcon2.......................................................... 100 inttreg.......................................................... 100 ipcx.................................................................. 100 interrupt vector table (ivt) ........................................ 97 reset sequence ................................................ ......... 97 setup procedures ..................................................... 134 initialization....................................................... 134 interrupt disable ............................................... 134 interrupt service routine.................................. 134 trap service routine........................................ 134 interrupts coincident with power save instructions ......... 148 j jtag boundary scan interface ....................................... . 267 jtag interface.................................................................. 272 m memory organization ............................................ ............. 43 microchip internet web site.............................................. 392 modulo addressing ............................................................. 75 applicability................................................................. 76 operation example ..................................................... 75 start and end address .............................................. . 75 w address register selection .................................... 75 mplab assembler, linker, librarian................................ 284 mplab icd 3 in-circuit debugger ................................... 285 mplab pm3 device programmer .................................... 285 mplab real ice in-circuit emulator system ................ 285 mplab x integrated development environment software .............................................. 283 mplab x sim software simulator ................................... 285 mplib object librarian..................................................... 284 mplink object linker ...................................................... 284 o open-drain configuration.............................................. ... 156 oscillator configuration ............... ..................................... 135 control registers ...................................................... 13 9 output compare ............................................................... 193 modes....................................................................... 194 operation diagram ................................................... 194 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 389 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 p packaging ......................................................................... 351 details ....................................................................... 353 marking ..................................................................... 351 peripheral module disable (pmd) .................................... 148 peripheral pin select (pps) .......................................... .... 157 pickit 3 in-circuit debugger/programmer ........................ 285 pinout i/o descriptions (table) ....................................... ..... 19 power-on reset (por) ....................................................... 94 power-saving features .................................................... 147 clock frequency and switching................................ 147 power-up timer (pwrt) .................................................... 94 pps control registers ...................................................... 16 1 selectable input sources .......................................... 158 selection output sources ......................................... 159 program address space ..................................................... 43 construction................................................................ 78 data access from program memory using program space visibility..................................... 81 data access from program memory using table instructions ............................................... 80 data access from, address generation...................... 79 memory maps ............................................................. 43 table read instructions tblrdh ............................................................. 80 tblrdl .............................................................. 80 visibility operation ...................................................... 81 program memory interrupt vector ........................................................... 44 organization.............................................. .................. 44 reset vector ............................................................... 44 r reference clock generation............................................ . 138 register maps analog comparator control for dspic33fj06gs202 ........................................... 67 analog comparator control for dspic33fj16gs503/504 .................................... 67 change notification for dspic33fj06gs101 ............. 51 change notification for dspic33fj06gs102/202 and dspic33fj16gs402/502 ............................. 51 change notification for dspic33fj16gs404/504 .................................... 51 cpu core.................................................................... 50 high-speed 10-bit adc for dspic33fj06gs101....... 63 high-speed 10-bit adc for dspic33fj06gs102....... 63 high-speed 10-bit adc for dspic33fj06gs202....... 64 high-speed 10-bit adc for dspic33fj16gs402/404 .................................... 64 high-speed 10-bit adc for dspic33fj16gs502....... 65 high-speed 10-bit adc for dspic33fj16gs504....... 66 high-speed pwm ....................................................... 59 high-speed pwm generator 1 ................................... 60 high-speed pwm generator 2 for dspic33fj06gs101/ 202 and dspic33fj16gsx02/x04 ..................... 60 high-speed pwm generator 3 for dspic33fj16gsx02/x04 ................................... 61 high-speed pwm generator 4 for dspic33fj06gs101 and dspic33fj16gs50x ................................... 61 i2c1 ............................................................................ 62 input capture for dspic33fj06gs202 ....................... 58 input capture for dspic33fj16gsx02/x04 ............... 59 interrupt controller for dspic33fj06gs101............... 52 interrupt controller for dspic33fj06gs102 .............. 53 interrupt controller for dspic33fj06gs202 .............. 54 interrupt controller for dspic33fj16gs402/404 ....... 55 interrupt controller for dspic33fj16gs502 .............. 56 interrupt controller for dspic33fj16gs504 .............. 57 nvm............................................................................ 71 output compare for dspic33fj06gs101/x02 .......... 59 output compare for dspic33fj16gsx02 and dspic33fj06gsx04 ................................... 59 pmd for dspic33fj06gs101 .................................... 71 pmd for dspic33fj06gs102 .................................... 71 pmd for dspic33fj06gs202 .................................... 72 pmd for dspic33fj16gs402/404 ............................. 72 pmd for dspic33fj16gs502/504 ............................. 72 porta ....................................................................... 70 portb for dspic33fj06gs101 ................................ 70 portb for dspic33fj06gs102/202 and dspic33fj16gs402/404/502/504............... 70 portc for dspic33fj16gs404/504......................... 70 pps input ................................................ ................... 68 pps output for dspic33fj06gs101 ......................... 68 pps output for dspic33fj06gs102/202 and dspic33fj16gs402/502............................. 69 pps output for dspic33fj16gs404/504 .................. 69 spi1............................................................................ 62 system control ........................................................... 71 timers for dspic33fj06gs101/x02 .......................... 58 timers for dspic33fj16gsx02/x04.......................... 58 uart1........................................................................ 62 registers aclkcon (auxiliary clock divisor control)............. 144 adbase (analog-to-digital base)............................ 250 adcon (analog-to-digital control) .......................... 247 adcpc0 (analog-to-digital convert pair control 0).......................................................... 251 adcpc1 (analog-to-digital convert pair control 1).......................................................... 254 adcpc2 (analog-to-digital convert pair control 2).......................................................... 257 adcpc3 (analog-to-digital convert pair control 3).......................................................... 260 adpcfg (analog-to-digital port configuration)....... 250 adstat (analog-to-digital status) .......................... 249 altdtrx (pwmx alternate dead-time).................. 210 clkdiv (clock divisor) ............................................ 141 cmpconx (comparator control x) .......................... 265 cmpdacx (comparator dac x control).................. 266 corcon (core control).................................... 36, 101 dtrx (pwmx dead-time)........................................ 210 fclconx (pwmx fault current-limit control)........ 214 i2cxcon (i2cx control)........................................... 228 i2cxmsk (i2cx slave mode address mask)............ 232 i2cxstat (i2cx status) ........................................... 230 icxcon (input capture x control)............................ 192 iec0 (interrupt enable control 0) ............................. 112 iec1 (interrupt enable control 1) ............................. 114 iec3 (interrupt enable control 3) ............................. 115 iec4 (interrupt enable control 4) ............................. 115 iec5 (interrupt enable control 5) ............................. 116 iec6 (interrupt enable control 6) ............................. 117 iec7 (interrupt enable control 7) ............................. 118 ifs0 (interrupt flag status 0) ................................... 105 ifs1 (interrupt flag status 1) ................................... 107 ifs3 (interrupt flag status 3) ................................... 108 ifs4 (interrupt flag status 4) ................................... 108 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 390 ? 2008-2014 microchip technology inc. ifs5 (interrupt flag status 5) ................................... 109 ifs6 (interrupt flag status 6) ................................... 110 ifs7 (interrupt flag status 7) ................................... 111 intcon1 (interrupt control 1).................................. 102 inttreg (interrupt control and status)................... 133 ioconx (pwmx i/o control) .................................... 212 ipc0 (interrupt priority control 0) ............................. 119 ipc1 (interrupt priority control 1) ............................. 120 ipc14 (interrupt priority control 14) ......................... 125 ipc16 (interrupt priority control 16) ......................... 125 ipc2 (interrupt priority control 2) ............................. 121 ipc23 (interrupt priority control 23) ......................... 126 ipc24 (interrupt priority control 24) ......................... 127 ipc25 (interrupt priority control 25) ......................... 128 ipc26 (interrupt priority control 26) ......................... 129 ipc27 (interrupt priority control 27) ......................... 130 ipc28 (interrupt priority control 28) ......................... 131 ipc29 (interrupt priority control 29) ......................... 132 ipc3 (interrupt priority control 3) ............................. 122 ipc4 (interrupt priority control 4) ............................. 123 ipc5 (interrupt priority control 5) ............................. 124 ipc7 (interrupt priority control 7) ............................. 124 lebconx (leading-edge blanking control) ............ 217 mdc (pwm master duty cycle) ............................... 204 nvmcon (flash memory control) ............................. 85 nvmkey (nonvolatile memory key) .......................... 86 ocxcon (output compare x control....................... 195 osccon (oscillator control) ................................... 139 osctun (frc oscillator tuning) ............................ 143 pdcx (pwmx generator duty cycle) ....................... 207 phasex (pwmx primary phase-shift) ..................... 208 pllfbd (pll feedback divisor) .............................. 142 pmd1 (peripheral module disable control 1) ........... 149 pmd2 (peripheral module disable control 2) ........... 150 pmd3 (peripheral module disable control 3) ........... 151 pmd4 (peripheral module disable control 4) ........... 151 pmd6 (peripheral module disable control 6) ........... 152 pmd7 (peripheral module disable control 7) ........... 153 ptcon (pwm time base control) .......................... 201 ptcon2 (pwm clock divider select) ...................... 203 ptper (pwm master time base)............................ 203 pwmcapx (primary pwmx time base capture)................................................... 218 pwmconx (pwmx control) ..................................... 205 rcon (reset control) ................................................ 90 refocon (reference oscillator control)................ 145 rpinr0 (peripheral pin select input 0) .................... 161 rpinr1 (peripheral pin select input 1) .................... 162 rpinr11 (peripheral pin select input 11) ................ 165 rpinr18 (peripheral pin select input 18) ................ 166 rpinr20 (peripheral pin select input 20) ................ 167 rpinr21 (peripheral pin select input 21) ................ 168 rpinr29 (peripheral pin select input 29) ................ 169 rpinr3 (peripheral pin select input 3) .................... 163 rpinr30 (peripheral pin select input 30) ................ 170 rpinr31 (peripheral pin select input 31) ................ 171 rpinr32 (peripheral pin select input 32) ................ 172 rpinr33 (peripheral pin select input 33) ................ 173 rpinr34 (peripheral pin select input 34) ................ 174 rpinr7 (peripheral pin select input 7) .................... 164 rpor0 (peripheral pin select output 0) .................. 174 rpor1 (peripheral pin select output 1).................. 175 rpor10 (peripheral pin select output 10).............. 179 rpor11 (peripheral pin select output 11).............. 180 rpor12 (peripheral pin select output 12).............. 180 rpor13 (peripheral pin select output 13).............. 181 rpor14 (peripheral pin select output 14).............. 181 rpor16 (peripheral pin select output 16).............. 182 rpor17 (peripheral pin select output 17).............. 182 rpor2 (peripheral pin select output 2).................. 175 rpor3 (peripheral pin select output 3).................. 176 rpor4 (peripheral pin select output 4).................. 176 rpor5 (peripheral pin select output 5).................. 177 rpor6 (peripheral pin select output 6).................. 177 rpor7 (peripheral pin select output 7).................. 178 rpor8 (peripheral pin select output 8).................. 178 rpor9 (peripheral pin select output 9).................. 179 sdcx (pwmx secondary duty cycle)...................... 207 sevtcmp (pwm special event compare) ............. 204 sphasex (pwmx secondary phase-shift).............. 209 spixcon1 (spix control 1)...................................... 221 spixcon2 (spix control 2)...................................... 223 spixstat (spix status and control) ....................... 220 sr (cpu status)............................................. 34, 101 strigx (pwmx secondary trigger compare value) ............................................... 216 t1con (timer1 control) .......................................... 184 trgconx (pwmx trigger control) ......................... 211 trigx (pwmx primary trigger compare value) ............................................... 216 txcon (timerx control, x = 2)................................. 188 tycon (timery control, y = 3)................................. 189 uxmode (uartx mode).......................................... 234 uxsta (uartx status and control)......................... 236 reset ................................................................................. . 89 configuration mismatch .............................................. 95 illegal condition ............................................. ............. 95 illegal opcode....................................................... 89, 95 security................................................................. 89, 96 system........................................................................ 92 trap conflict ............................................................... 95 uninitialized w register.................................. 89, 95, 96 resets................................................................................. 89 resources required for digital phase-shift zvt converter ............................................................ 30 revision history................................................................ 373 s serial peripheral interface (spi) ....................................... 219 software reset instruction (swr) ................................... 95 software stack pointer, frame pointer call stack frame ..................................................... 73 special features of the cpu ............................................ 267 symbols used in opcode descriptions ............................ 276 t temperature and voltage specifications ac..................................................................... 300, 338 timer1............................................................................... 183 timer2/3............................................................................ 185 16-bit operation ....................................................... 186 32-bit operation ....................................................... 186 downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 391 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 timing diagrams analog-to-digital conversion per input ..................... 329 brown-out situations................................................... 94 external clock........................................................... 301 high-speed pwmx ................................................... 311 high-speed pwmx fault .......................................... 311 i/o ............................................................................. 304 i2cx bus data (master mode) .................................. 324 i2cx bus data (slave mode) ................................... . 326 i2cx bus start/stop bits (master mode) ................... 324 i2cx bus start/stop bits slave mode) ...................... 326 input capture x (icx)........................................... ...... 309 ocx/pwmx ............................................................... 310 output compare x (ocx) .......................................... 309 reset, watchdog timer, oscillator start-up timer and power-up timer ......................................... 305 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) ........................................... 315 spix master mode (full-duplex, cke = 1, ckp = x, cmp = 1) ........................................... 314 spix master mode (half-duplex, transmit only, cke = 0)................................... 312 spix master mode (half-duplex, transmit only, cke = 1)................................... 312 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) ........................................... 322 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) ........................................... 320 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) ........................................... 316 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) ........................................... 318 system reset.............................................................. 93 timer1, 2, 3 external clock....................................... 307 timing requirements 10-bit, high-speed adc requirements.................... 329 external clock............................................... .... 301, 345 i/o ............................................................................. 304 input capture x ............................................. ............ 309 simple ocx/pwmx mode ......................................... 345 spix master mode (cke = 0) ................................... 339 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) ........................................... 315 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) ........................................... 314 spix master mode (half-duplex, transmit only) .................................................. 313 spix module master mode (cke = 1)....................... 339 spix module slave mode (cke = 0)......................... 340 spix module slave mode (cke = 1)......................... 340 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) ........................................... 323 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) ........................................... 321 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) ........................................... 317 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) ........................................... 319 timing specifications 10-bit high-speed adc module............................... 328 auxiliary pll clock................................................... 302 comparator module.............................................. .... 330 dac module ............................................................. 330 dac output buffer dc ............................................. 331 high-speed pwmx requirements............................ 311 i2cx bus data requirements (master mode)........... 325 i2cx bus data requirements (slave mode)............. 327 output compare x requirements............................. 309 pll clock ......................................................... 302, 338 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ................................................ ... 306 simple ocx/pwmx mode requirements ................. 310 timer1 external clock requirements ....................... 307 timer2 external clock requirements ....................... 308 timer3 external clock requirements ....................... 308 u universal asynchronous receiver transmitter (uart) .................................................. 233 using the rcon status bits............................................... 96 v voltage regulator (on-chip) ............................................ 270 w watchdog timer (wdt)......................................... ... 267, 271 programming considerations ................................... 271 watchdog timer time-out reset (wdto) ......................... 95 www address ................................................................. 392 www, on-line support ....... .............................................. 14 downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 392 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 393 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 394 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 395 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . architecture: 33 = 16-bit digital signal controller flash memory family: fj = flash program memory, 3.3v product group: gs1 = switch mode power supply (smps) family gs2 = switch mode power supply (smps) family gs4 = switch mode power supply (smps) family gs5 = switch mode power supply (smps) family pin count: 01 = 18-pin 02 = 28-pin 04 = 44-pin speed 50 = 50 mips temperature range: i = -40 ? c to+85 ? c (industrial) e=- 4 0 ? c to+125 ? c (extended) h=- 4 0 ? c to+150 ? c (high) package: pt = plastic thin quad flatpack - 10x10x1 mm body (tqfp) ml = plastic quad flat, no lead package - 8x8 mm body (qfn) mm = plastic quad flat, no lead package - 6x6x0.9 mm body (qfn-s) so = plastic small outline - wide - 7.50 mm body (soic) sp = skinny plastic dual in-line - 300 mil body (spdip) tl = very thin leadless array - 6x6 mm body (vtla) examples: a) dspic33fj06gs102-e/sp: smps dspic33, 6-kbyte program memory, 28-pin, extended temperature, spdip package. microchip trademark architecture flash memory family program memory size (kbyte) product group pin count speed (if applicable) package pattern dspic 33 fj 06 gs1 02 t - 50 e / sp - xxx tape and reel flag (if applicable) temperature range downloaded from: http:/// dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds70000318g-page 396 ? 2008-2014 microchip technology inc. notes: downloaded from: http:/// ? 2008-2014 microchip technology inc. ds70000318g-page 397 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2008-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-63276-216-0 note the following details of the code protection feature on microchip devices: microchip products meet the specification contai ned in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:/// ds70000318g-page 398 ? 2008-2014 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 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